license problem with xcelium 19.03

Hi all, 
i am running a mix-mode circuit (PLL) using xcelium & ultrasim 

the license for xcelium is available from the capture below but it seems cannot detect the license 

i already set $AMS_HOME to xcelium directory tools/bin & CDS_LIC_FILE for its but it seems not to obtain license file during simulation 

could anyone help to point our the culprit ? or any check that i can do, if y need further infor please let me know 
 

xrun log is attached here with license status from lmstat command 

xcelium version: 19.03 

ic version: 6.1.7 

spectre version: 17.1 

Appreciate much your help! 

Tommy

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xrun(64): 19.03-s019: (c) Copyright 1995-2020 Cadence Design Systems, Inc. TOOL: xrun(64) 19.03-s019: Started on Jun 13, 2023 at 03:13:58 EDT xrun -f xrunArgs -UNBUFFERED -cdslib ./cds.lib -errormax 50 -status -nowarn DLNOHV -nowarn DLCLAP -v93 -incdir "/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/" -ade -timescale 1ns/1ns -vtimescale 1ns/1ns -discipline logic -delay_mode None -novitalaccl -access r -noparamerr -amspartinfo ../psf/partition.info -rnm_partinfo -amsfastspice -modelincdir /projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/ ./spiceModels.scs ./amsControlUltraSim.scs -input ./probe.tcl -run -exit -xmsimargs "+amsrawdir ../psf" -spectre_args "-ahdllibdir /home/khant/simulation/kha_ibm_testchip_sim/sim_PLL_TOP_netlist_reduced/maestro/results/maestro/ExplorerRun.0/sharedData/Job6/ahdl/input.ahdlSimDB" -simcompatible_ams spectre -name kha_ibm_testchip_sim.sim_PLL_TOP_netlist_reduced:config -amsconnrules ConnRules_18V_full_fast +define+CDS_SELECT_CRS +define+CONNRULES_18V_FULL_FAST /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_basic/connect/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2L_2/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/Bidir_2/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2R/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2E_2/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ER_bidir/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2L/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2R/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/RL_bidir/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2_CPF/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/Bidir_2_CPF/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2L_2_CPF/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2L_CPF/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2R_CPF/module/verilog.vams /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/RL_Bidir_CPF/module/verilog.vams -allowredefinition -amsbind -top kha_ibm_testchip_sim.sim_PLL_TOP_netlist_reduced:schematic -top cds_globals ./netlist.vams -f ./textInputs -amscompilefile "file:/sw2/tools/Cadence/IC617.722/tools.lnx86/dfII/samples/artist/ahdlLib/vco/veriloga/veriloga.va ftype:va lib:ahdlLib cell:vco view:veriloga" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/NRF40_UTILS/adc6b/veriloga/veriloga.va ftype:va lib:NRF40_UTILS cell:adc6b view:veriloga" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/kha_ibm_testchip_sim/vco_tune/functional/verilog.v lib:kha_ibm_testchip_sim cell:vco_tune view:functional" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/kha_ibm_testchip_sim/mash111_20/functional/verilog.v lib:kha_ibm_testchip_sim cell:mash111_20 view:functional" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/NRF40_UTILS/adc24b/veriloga/veriloga.va ftype:va lib:NRF40_UTILS cell:adc24b view:veriloga" -amscompilefile "file:/sw2/tools/Cadence/IC617.722/tools.lnx86/dfII/samples/artist/ahdlLib/amp/veriloga/veriloga.va ftype:va lib:ahdlLib cell:amp view:veriloga" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/NRF40_UTILS/adc3b/veriloga/veriloga.va ftype:va lib:NRF40_UTILS cell:adc3b view:veriloga" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/NRF40_UTILS/adc4b/veriloga/veriloga.va ftype:va lib:NRF40_UTILS cell:adc4b view:veriloga" -amscompilefile "file:/projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/kha_ibm_testchip_sim/nrc5291_vcocal_dsm/functional/verilog.v lib:kha_ibm_testchip_sim cell:nrc5291_vcocal_dsm view:functional" -makelib ibm_testchip_R0 -makelib ibm_testchip_R0 -makelib ibm_testchip_R1 -makelib ibm_testchip_R1 -makelib ibm_testchip -makelib NRF40_HYBRID_CAP -makelib ibm_testchip_R1 -endlib ./cds_globals.vams -l ../psf/xrun.log file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_basic/connect/verilog.vams connect worklib.ConnRules_18V_full_fast:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2/module/verilog.vams $SIE_input(Din, Dval); // set digital driver sensitivity | xmvlog: *W,NOSYST (/sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2/module/verilog.vams,116|12): System function '$SIE_input' invoked as a task. Return value will be ignored. module worklib.L2E_2:vams errors: 0, warnings: 1 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2L_2/module/verilog.vams $SIE_input(Dout, Dval); //set digital driver sensitivity | xmvlog: *W,NOSYST (/sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2L_2/module/verilog.vams,54|13): System function '$SIE_input' invoked as a task. Return value will be ignored. module worklib.E2L_2:vams errors: 0, warnings: 1 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/Bidir_2/module/verilog.vams $SIE_input(Din, Dval); //set digital driver sensitivity | xmvlog: *W,NOSYST (/sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/Bidir_2/module/verilog.vams,137|13): System function '$SIE_input' invoked as a task. Return value will be ignored. module worklib.Bidir_2:vams errors: 0, warnings: 1 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2R/module/verilog.vams module worklib.E2R:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2E_2/module/verilog.vams module worklib.R2E_2:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ER_bidir/module/verilog.vams $input_real_value(Din, R_val); | xmvlog: *W,NOSYST (/sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ER_bidir/module/verilog.vams,41|24): System function '$input_real_value' invoked as a task. Return value will be ignored. module worklib.ER_bidir:vams errors: 0, warnings: 1 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2L/module/verilog.vams module worklib.R2L:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2R/module/verilog.vams module worklib.L2R:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/RL_bidir/module/verilog.vams $input_real_value(R, R_val); // set real driver sensativity | xmvlog: *W,NOSYST (/sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/RL_bidir/module/verilog.vams,28|17): System function '$input_real_value' invoked as a task. Return value will be ignored. module worklib.RL_bidir:vams errors: 0, warnings: 1 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2E_2_CPF/module/verilog.vams module worklib.L2E_2_CPF:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/Bidir_2_CPF/module/verilog.vams module worklib.Bidir_2_CPF:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/E2L_2_CPF/module/verilog.vams module worklib.E2L_2_CPF:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2L_CPF/module/verilog.vams module worklib.R2L_CPF:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/L2R_CPF/module/verilog.vams module worklib.L2R_CPF:vams errors: 0, warnings: 0 file: /sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/RL_Bidir_CPF/module/verilog.vams $input_real_value(R, R_val); // set real driver sensitivity | xmvlog: *W,NOSYST (/sw2/cadence/INCISIV13.10_/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/RL_Bidir_CPF/module/verilog.vams,43|24): System function '$input_real_value' invoked as a task. Return value will be ignored. module worklib.RL_Bidir_CPF:vams errors: 0, warnings: 1 file: ./netlist.vams module ibm_testchip_R1.BUFFD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_CP_switch_FiltRst:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_schmitt:schematic errors: 0, warnings: 0 module ibm_testchip_R1.AN2D2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD2BWPHVT_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD8BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.BUFFD2BWPHVT_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.AN4D2BWPHVT_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_DECODER_4TO16HVT_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD8BWP_lvt_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD1BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.ND2D1BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.MUX4D4BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.ND2D2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_PFD_11ah_VAR_DLY:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_CP_11ah_Ict_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.AN2D4BWP_lvt_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.NR2XD1BWP_lvt_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.DFCND4BWP_lvt_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD4BWP_lvt_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_PFD_11ah_core_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_PFD_11ah_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_CP_11ah_isw_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_CP_11ah_BLDR_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.OR2D1BWP:schematic errors: 0, warnings: 0 module ibm_testchip_R1.AN2D2BWPHVT_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD4BWPHVT_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_VCO_buffer_spi_NRC5292:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_CP_11ah_AMP_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LO_MUX:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD4BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_VM_rsw_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_switch_v03_vm:schematic errors: 0, warnings: 0 module ibm_testchip_R1.BUFFD8BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_comp_v01:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_comp_v02:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_VM_rsw_ref_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_LF_11ah_buf_NRC5291:schematic errors: 0, warnings: 0 module NRF40_HYBRID_CAP.HBCAP_PMOS33_UNIT_1p:schematic errors: 0, warnings: 0 module kha_ibm_testchip_sim.PLL_CP_11ah_NRC5291:schematic errors: 0, warnings: 0 module kha_ibm_testchip_sim.PLL_LF_11ah_VMONITOR_NRC5291:schematic errors: 0, warnings: 0 module kha_ibm_testchip_sim.sim_PLL_TOP_netlist_reduced:schematic errors: 0, warnings: 0 module kha_ibm_testchip_sim.PLL_VCO_buffer_top_NRC5292:schematic errors: 0, warnings: 0 module ibm_testchip.PLL_MMD_11ah_INV2_lvt:schematic errors: 0, warnings: 0 module ibm_testchip.PLL_MMD_11ah_ND2_lvt:schematic errors: 0, warnings: 0 module ibm_testchip.PLL_MMD_11ah_DFFRHQ_lvt:schematic errors: 0, warnings: 0 module ibm_testchip.HBCAP_NMOS33_UNIT_2term_1p_dnw_m6:schematic errors: 0, warnings: 0 module ibm_testchip.INV1_HV_33V_DNW:schematic errors: 0, warnings: 0 module ibm_testchip.HBCAP_PMOS33_UNIT_1p:schematic errors: 0, warnings: 0 module ibm_testchip.HBCAP_PMOS33_UNIT_BGR_1p:schematic errors: 0, warnings: 0 module ibm_testchip_R1.AN2D4BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD0BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.BUFFD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.INVD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.BUFFD8BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R1.PLL_MR_PLL1P2LDO_v03:schematic errors: 0, warnings: 0 module ibm_testchip_R0.BUFFD8BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_switch_v03:schematic errors: 0, warnings: 0 module ibm_testchip_R0.INVD4BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_rsw_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_csw2_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.BUFFD4BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.INVD8BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_rsw_3x_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_csw3_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.INVD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_switch_v03_vforce:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_VM_RSW_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_buf_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_csw4_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.BUFFD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_csw1_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_rsw3_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_LF_11ah_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_11ah_INV8:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_11ah_tgate:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_PWRSW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_11ah_AND2:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_ND4_lvt:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_div23_C2MOS_2nd:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_11ah_INV4:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_11ah_div23_C2:schematic errors: 0, warnings: 0 module ibm_testchip_R0.HBCAP_PMOS33_UNIT_2term_1p:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_VCO_buffer_lo_rx:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_VCO_buffer_inv8_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_VCO_buffer_inv4_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_VCO_buffer_core_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_MMD_INV4_lvt:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_SBR_DIV4_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_PWRSW_BUF_NRC5291:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_VCO_buffer_lo_tx:schematic errors: 0, warnings: 0 module ibm_testchip_R0.PLL_VCO_buffer_out_dr:schematic errors: 0, warnings: 0 module ibm_testchip_R0.WBGR_Current_trim:schematic errors: 0, warnings: 0 module ibm_testchip_R0.INVH_BGR_r00:schematic errors: 0, warnings: 0 module ibm_testchip_R0.WBGR_CORE_R0:schematic errors: 0, warnings: 0 module ibm_testchip_R0.test_bgrbias:schematic errors: 0, warnings: 0 module ibm_testchip_R0.HBCAP_NMOS33_UNIT_1p_dnw:schematic errors: 0, warnings: 0 module ibm_testchip_R0.BUFFD2BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.AN2D4BWP_DNW:schematic errors: 0, warnings: 0 module ibm_testchip_R0.INVD0BWP_DNW:schematic errors: 0, warnings: 0 file: ./cds_globals.vams module worklib.cds_globals:vams errors: 0, warnings: 0 file: /projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/kha_ibm_testchip_sim/vco_tune/functional/verilog.v module kha_ibm_testchip_sim.vco_tune:functional errors: 0, warnings: 0 file: /projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/kha_ibm_testchip_sim/mash111_20/functional/verilog.v module kha_ibm_testchip_sim.mash111_20:functional errors: 0, warnings: 0 file: /projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/kha_ibm_testchip_sim/nrc5291_vcocal_dsm/functional/verilog.v module kha_ibm_testchip_sim.nrc5291_vcocal_dsm:functional errors: 0, warnings: 0 xmvlog: *W,SPDUSD: Include directory /projects/siso40n/design/khant/ICM_WS/khant+NRF40ULP+RTC01+2/ given but not used. Total errors/warnings found outside modules and primitives: errors: 0, warnings: 1 xmvlog: Memory Usage - Current physical: 19.3M, Current virtual: 62.6M xmvlog: CPU Usage - 0.0s system + 0.2s user = 0.2s total (1.0s, 18.2% cpu) Caching library 'ibm_testchip_R0' ....... Done Caching library 'ibm_testchip_R1' ....... Done Caching library 'kha_ibm_testchip_sim' ....... Done Caching library 'ibm_testchip_R0' ....... Done Caching library 'ibm_testchip_R1' ....... Done Caching library 'ibm_testchip' ....... Done Caching library 'worklib' ....... Done Caching library 'NRF40_HYBRID_CAP' ....... Done Caching library 'ibm_testchip_R1' ....... Done Elaborating the design hierarchy: Caching library 'ibm_testchip_R1' ....... Done Caching library 'worklib' ....... Done Caching library 'ibm_testchip_R0' ....... Done Caching library 'ibm_testchip_R0' ....... Done Caching library 'ibm_testchip_R1' ....... Done Caching library 'ibm_testchip_R1' ....... Done Caching library 'ibm_testchip' ....... Done Caching library 'NRF40_HYBRID_CAP' ....... Done Top level design units: sim_PLL_TOP_netlist_reduced cds_globals Discipline resolution Pass... xmelab: *W,MSPIEV: [LPS] The program encountered the power aware vpi task ($amscpf_power_state_register) which will be deprecated in future release. xmelab: *W,MSPIEV: [LPS] The program encountered the power aware vpi task ($amscpf_power_state_register) which will be deprecated in future release. xmelab: *W,MSPIEV: [LPS] The program encountered the power aware vpi task ($amscpf_power_state_register) which will be deprecated in future release. xmelab: *W,MSPIEV: [LPS] The program encountered the power aware vpi task ($amscpf_power_state_register) which will be deprecated in future release. xmelab: *W,MSPIEV: [LPS] The program encountered the power aware vpi task ($amscpf_power_state_register) which will be deprecated in future release. xmelab: *W,MSPIEV: [LPS] The program encountered the power aware vpi task ($amscpf_power_state_register) which will be deprecated in future release. Doing auto-insertion of connection elements... Connect Rules applied are: ConnRules_18V_full_fast Building instance overlay tables: .................... Done Generating native compiled code: ibm_testchip_R0.WBGR_CORE_R0:schematic streams: 0, words: 0 kha_ibm_testchip_sim.mash111_20:functional streams: 63, words: 18353 kha_ibm_testchip_sim.vco_tune:functional streams: 39, words: 20656 kha_ibm_testchip_sim.sim_PLL_TOP_netlist_reduced:schematic streams: 0, words: 0 worklib.E2L_2:vams streams: 6, words: 5750 worklib.L2E_2:vams streams: 4, words: 5965 Building instance specific data structures. Loading native compiled code: .................... Done Design hierarchy summary: Instances Unique Modules: 1623 136 Registers: 373 157 Scalar wires: 184 - Expanded wires: 6 1 Vectored wires: 97 - Always blocks: 414 91 Initial blocks: 82 29 Cont. assignments: 32 60 Interconnect: 6159 - Simulation timescale: 1ps Writing initial simulation snapshot: kha_ibm_testchip_sim.sim_PLL_TOP_netlist_reduced:config xmelab: Memory Usage - Final: 56.0M, Peak: 228.2M, Peak virtual: 333.7M xmelab: CPU Usage - 0.1s system + 0.5s user = 0.6s total (1.5s, 37.7% cpu) xmsim: *W,OPOBSO: Obsolete option AMSLIC: Use AMS license. xmsim: *W,ENVDEPRREN: Environment Variable (NCSIMOPTS) is deprecated. Use (XMSIMOPTS) instead. AMS_Connector 16.10 - license checkout failed Virtuoso_Multi_mode_Simulation 16.10 - license checkout failed xmsim: *F,NOLICN: Unable to checkout license for the simulation. 'lic_error -4'. xmsim: Memory Usage - Final: 14.0M, Peak: 14.5M, Peak virtual: 134.0M xmsim: CPU Usage - 0.0s system + 0.0s user = 0.0s total (18.7s, 0.2% cpu) TOOL: xrun(64) 19.03-s019: Exiting on Jun 13, 2023 at 03:14:34 EDT (total: 00:00:36) ===============================================================