How to prevent "Package cannot be bound" error when running check and save on a systemVerilog file

I am able to compile and run my testbench by adding DEFINE XRUNOPTS -incdir ... to my HDL.var file for any packages that I have in my code.  The problem I have however is that I still get the package cannot be bound error when I check and save my file.  This is preventing me from checking the rest of the errors that may exist in my systemVerilog file as no errors after the package include are checked.  How can I get the check and save option to not display this error?

I found the following post however I never found a final answer to the check and save issue which appears the same as what I have.

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/55508/virtuoso-systemverilog-errors#

I understand this to be an issue where the package files must be pre-compiled.  When I use the HDL Package setup to compile the packages, I can get the errors on check and save to temporarily go away however it always comes back.  Is there a way I can permanently compile these packages to a known location where they can be recalled on future check and saves so I do not have to constantly rerun the HDL Package setup?

Thanks,

Brian