i am using gpdk045 technology and i want to get the value of the capacitance

The value of the capacitance of what? Your question is not really a question that makes a great deal of sense - you're going to have to provide some more information.

Andrew

 i want to know the tox value of this  technology( transistor gate oxide thickness)

Looking at models/spectre/gpdk045_mos.scs , the oxide thickness is 2.41nm (for NMOS) and 2.4nm (for PMOS) for the typical process corner. It varies a little either side of that over corners.

Andrew

Dear Hagar Hendy.

I wrote my response last evening, but I'm having some trouble logging into the new system as it occasionally never responds after I enter my credentials. It is working today, however, so felt I might add a little information.

Hagar Hendy said:

nd i want to get the value of the capacitance using 

Κ ϵ0/tox  where is the relative permittivity , ϵ0 is the permittivity of free space, and tox is the transistor gate oxide thickness

Writing for myself, I do not understand what specifically you are trying to determine. The gate capacitance is composed of a number of  individual capacitances - only one of which is due to the simple relationship

you show. Further, the gate capacitance of an MOS device is not constant with bias nor frequency as originally computed and published by Goetzberger in 1966 in reference [1].

In other words, knowing the capacitance associated with only the term may not relate to the actual gate capacitance for a device.

Shawn


[1]. Goetzberger, Adolf Prof Dr. “Ideal mos curves for silicon.” Bell System Technical Journal 45 (1966): 1097-1122.

I am trying to verify the below equation theoretically to get the delay and comparing with the simulation results, Because of that I need the above parameters as shown below, the capacitance here is not explicit.

the delay between the two inverters 

It's going to be more complex than just the gate capacitance - there's also the other junction capacitances, plus parasitics on the interconnect (I'm not sure what that equation is trying to describe - it's not that clear).

Andrew

It's going to be more complex than just the gate capacitance - there's also the other junction capacitances, plus parasitics on the interconnect (I'm not sure what that equation is trying to describe - it's not that clear).

Andrew

Dear Hagar Hendy,

Hagar Hendy said:

I am trying to verify the below equation theoretically to get the delay and comparing with the simulation results, Because of that I need the above parameters as shown below, the capacitance here is the parastic capacitance and not explicit.

My apologies for my delayed response, but I seem to be having trouble with the new Cadence login process as it is not responding after I enter my credentials. I wrote this last evening and am just now able to log in successfully and post it.

As Andrew correctly mentioned, using a model of a single capacitor value and a single resistor value where the capacitance represents a version of some capacitance and the resistance that contained in the sources of your inter -buffer loads to model the effective time constant is likely not sufficient to accurately model the time constant. As shown in Figure 1, the gate capacitance of your inter-buffer devices will vary with time as the switching voltage changes and is frequency dependent. Further, you have not included any resistance in your equation for drain-source resistance nor trace path resistance.

What I might suggest is you perform a small signal AC or transient simulation to determine the impedance of your inter-buffer load as a function of the bias level on its drain and the control signal on its gate using  a est bench similar to the example shown in Figure 2. Sweep the frequency as well as the two DC voltages and then you can compute the real and imaginary parts of the input impedance Zin. This will provide the effective resistance and capacitance of your load as a function of its terminal voltages.

Running a transient simulation in lieu of the AC simulation will provide a more exact effective resistance and capacitance if you modify the test bench to include the buffer output voltage as a function of time and remove the DC bias voltage. You will run a single transient simulation at each frequency that you wish to measure the real and imaginary impedances.

I hope this helps and makes some sense Hagar Hendy!

Shawn

Figure 1

Figure 2

Sorry for the late reply, I have a question, is the previous method that used to measure the equivalent resistance and capacitance as Norton or Thevenin equivalent circuit?

For the current source, I could choose sin wave. and for the DC bias, what value should I put and why? 

for the resistor, is there a type of Ac resistor that I have to select?, I want to get the real and imaginary parts separately 

could you please check the below, my goal is to find the impedance for the circuit,  for example, there are four parallel branches in the circuit. i want to measure the effective impedance, and leakage current through the off transistor, and if parallel branches for example are increased to 12, what will be the equivalent impedence, and how will effect the delay of the circuit? 

Dear Hagar Hendy,

Hagar Hendy said:

I have a question, is the previous method that used to measure the equivalent resistance and capacitance as Norton or Thevenin equivalent circuit?

When you measure the input impedance of a network as shown in Figure 2 of my prior Forum post, the result will generally have real and imaginary parts and will be frequency dependent. As such, the real and imaginary parts are mathematically summed together and hence correspond to a Thevenin equivalent network as shown in Figure 3.

Figure 3

Hagar Hendy said:

For the current source, I could choose sin wave. and for the DC bias, what value should I put and why? 

If you planning to perform an AC small-signal analysis, set the current source to an AC value of 1. If you are planning to perform a large signal transient analysis to examine the effective large signal impedance, set the current source to a sinusoid with an amplitude that results in a voltage swing that mimics the voltage range when used in your actual circuit. This assures the voltages seen by the active components is similar to that seen in actual circuit operation.

For small-signal AC analyses, I would suggest setting the DC bias to a variable and sweeping its value from, for example, ground to your positive supply in some number of increments. This allows you to see how the impedance changes as the voltage across your network changes.

For a large signal transient, if your current source amplitude is set to provide the maximum and minimum voltage values across your network, then there is no need for a DC bias. A DC bias is only necessary in a transient impedance simulation if the sinusoidal current amplitude results in a voltage swing that is far less than the swing in actual circuit operation.

Hagar Hendy said:

for the resistor, is there a type of Ac resistor that I have to select?, I want to get the real and imaginary parts separately 

If you choose an ideal resistor from analogLib, there is an option to set a value for its AC value. Hence, choose a small DC value (<< 1 ohm) and set the AC value to a large value (say 1e12). In this fashion, it will appear as an open for your small-signal AC simulations and a short circuit for the DC operating point computation. Hence, this allows you to set the DC bias in a small-signal AC impedance simulation without the DC source shorting out the AC impedance of your network. The resulting AC impedance will, in general, be complex and you can access its real and imaginary parts using the Calculator real() and imaginary() functions respectively.

Hagar Hendy said:

for example, there are four parallel branches in the circuit. i want to measure the effective impedance, and leakage current through the off transistor, and if parallel branches for example are increased to 12, what will be the equivalent impedence, and how will effect the delay of the circuit? 

Treating your network as a "black box" and use the technique I outlined in my prior post will provide the impedance of the network - whether it has 4 branches shown in your screenshot or if you extend it to 12 branches. With the impedance computed from your simulation(s), you can estimate the impact of the network on your delay through its effective impedance and its driving and terminating impedances.

I hope I understood your questions correctly and the responses make some sense to you Hagar Hendy!

Shawn

Thank you so much, yes you understood my question, what I want to show you if i understand the steps that you said or not ,and i am doing right or not ?

i am trying to do a small signal analysis: for the current source I choose the dc current source and I put 1 A  at the AC value as shown in the screenshot.  For the resistor when i  put << 1 ohm, it gives an error so I chose a value less than 1 for example 0.8, For AC setup is shown below, please check it  if the setup is right 

and this the graph that results, which i didn't understand, i think i am doing something wrong 

Dear Hagar Hendy,

Hagar Hendy said:

yes you understood my question,

Great - at least I did that much right anyway!

Hagar Hendy said:

what I want to show you if i understand the steps that you said or not ,and i am doing right or not ?

i am trying to do a small signal analysis: for the current source I choose the dc current source and I put 1 A  at the AC value as shown in the screenshot.  For the resistor when i  put << 1 ohm, it gives an error so I chose a value less than 1 for example 0.8,

You set the current source correctly.

However, perhaps there is some confusion on how to set the resistor values. You should not get an error when setting its DC value to something << 1. As an example, Figure 4 shows how to set the DC resistance to 1 milliohm and the AC resistance (circled in red) to 1e12. Setting the DC resistance to 1 milliohm does not result in an error. Did you set the AC resistance to something large in your simulation?

Figure 4.

Hagar Hendy said:

For AC setup is shown below, please check it  if the setup is right 

It appears you are using ADE-L. This is no longer supported by Cadence. I would seriously consider migrating to ADE Assembler/Explorer. Explorer is very similar to the interface for ADE-L and has far more features and capabilities than ADE-L. The migration process is very easy to convert your state file to the new maestro view that is shared by Assembler and Explorer.

For your AC simulation GUI, it appears you are attempting to simulate the impedance at 1 MHz and sweeping the value of design variable "var". Is there a reason you only want to see the impedance at 1 MHz? It can be instructive to see how the impedance varies with frequency. Nevertheless, your basic AC setup appears fine.

Hagar Hendy said:

and this the graph that results, which i didn't understand, i think i am doing something wrong 

I do not know your test bench nor the impedance you are simulating. Hence, I cannot tell you if what you plotted is "correct" or even what it means. Is /net1 the positive node of your AC current source? If /net1 is the positive node of your current source, then the plot is the magnitude of the impedance.  If so, the plot suggests is that as you swept variable "var" from 0.0 to 1.0, the magnitude the impedance varies from about 0.25e6 at var = 0 to 7.5e6 at var = 1.

To determine the real and imaginary parts, you need to plot the real and imaginary parts of the response at node /net1 - not the magnitude. Use the Results Browser to send output node /net1 to the Calculator and make use of the real() and imaginary functions of the Calculator to plot each. If you are interested in the effective capacitance, you will need to compute it from the imaginary part of the impedance using the 1 MHz simulation frequency. This can all be automated as you can create an output that contains the real impedance and a second output that contains the effective capacitance.

Shawn

Dear Hagar Hendy,

Unfortunately, my response was characterized as "spam". Hopefully, it will be released soon. However, I thought you ay also be interested in a prior Forum post where I included expressions for the real and equivalent capacitance for an impedance element using a similar test bench. At the time, to my knowledge, an AC resistor was not available so I used a large inductor to isolate the DC and AC frequencies. However, I recommend you use an AC resistor. An updated version of the test bench I used to determine the impedance of an arbitrary network is also attached.

https://community.cadence.com/cadence_technology_forums/f/rf-design/38996/capacitance-vs-bias-voltage-curve-for-ferroelectric-varactor