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  3. xmvlog cannot complie or recoganize genvar and generate

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xmvlog cannot complie or recoganize genvar and generate

Biasing
Biasing over 1 year ago

Dear all,

We are using XRUN to run the AMS simulation. In one of your Verilog building block, the instances are instantiated using genvar and generate block,as shown below:

// Inst. of stage0 spi_mux8
genvar i;
generate
for (i=0; i<7; i=i+1)
begin: GEN_U_SPI_MUX8_S0

spi_mux8
U_SPI_MUX8_S0
(
.i_dat (ext_dat[(i+1)*8-1:i*8] ),
.sel (sel[2:0] ),
.o_dat (mux_dat[i] )
);

end
endgenerate

When we run the AMS simulation, the following error pops up:

xmelab: *F,OSDINF (/home/jxing/proj/spi_mux50/functional/verilog.v,25|16): instance 'TB_top.I0@top_5050<module>.I3@core_5050<module>.I9@spi_top<module>.U_SPI_MUX50_VLD@spi_mux50<module>.GEN_U_SPI_MUX8_S0[0].U_SPI_MUX8_S0' of design unit 'spi_mux8' is a leaf instance and is unresolved in cellview 'ussuri_digital_5050.spi_mux50:functional'. Ensure that the design unit is either pre-compiled or its corresponding text file is specified for compilation. Also, check the binding for this instance in Cadence Hierarchy Editor to confirm if it is set to externalHDL or addStopPoint or if nlAction is set to 'stop' for the specified instance.

I guess this is because xmvlog only supports Verilog-95 since generate block is introduced in Verilog-2001

When we instantiated the blocks in the old way, as shown below. no error pops up and the simulation could continue.

spi_mux8
U_SPI_MUX8_S0
(
.i_dat (ext_dat[7:0] ),
.sel (sel[2:0] ),
.o_dat (mux_dat[1] )
);

spi_mux8
U_SPI_MUX8_S0
(
.i_dat (ext_dat[15:8] ),
.sel (sel[2:0] ),
.o_dat (mux_dat[2] )
);

Does anyone have similar experience or issue when doing the AMS simulation?

We are using IC618 and XCELIUM1803

Best regards,

Chris

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