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  3. How to set a parameter in a Verilog module as a variable...

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How to set a parameter in a Verilog module as a variable, and send it to the ADE Explorer to scan its different values in simulation?

wangyunxin
wangyunxin over 1 year ago


I named the parameter k in Verilog as ki, and gave it four different parameter values in the simulation: 20'b00000100000000000000, 20'b00001000000000000000, 20'b00010000000000000000, 20'b00100000000000000000, 20'b01000000000000000000. I wanted to see the simulation results of the circuit system under these four parameters, but ADE reported the following error. How can I solve this?
and Will adding quotation marks allow me to carry out my parameter scan?

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  • wangyunxin
    wangyunxin over 1 year ago

    Based on the simulation result chart, it seems that changing the string parameter did not have an effect. What would be the correct approach?

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  • ShawnLogan
    ShawnLogan over 1 year ago in reply to wangyunxin

    Dear wangyunxin,

    wangyunxin said:
    I named the parameter k in Verilog as ki, and gave it four different parameter values in the simulation: 20'b00000100000000000000, 20'b00001000000000000000, 20'b00010000000000000000, 20'b00100000000000000000, 20'b01000000000000000000. I wanted to see the simulation results of the circuit system under these four parameters, but ADE reported the following error. How can I solve this?

    First of all, you mentioned changing the variable ki to 4 values,, but then listed five string values. I assume you intended to change it to each of the 5 values?

    If so, have you tried changing your definition of variable to ki to:

    strcat("20'b00000100000000000000" "20'b00001000000000000000" "20'b00010000000000000000" "20'b00100000000000000000" "20'b01000000000000000000")

    You may need to escape the single quotation mark you included in the string, but I am not sure and am unable to test the expression.

    Shawn

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  • Andrew Beckett
    Andrew Beckett over 1 year ago in reply to ShawnLogan
    ShawnLogan said:
    strcat("20'b00000100000000000000" "20'b00001000000000000000" "20'b00010000000000000000" "20'b00100000000000000000" "20'b01000000000000000000")

    That's not going to work as it will just generate a single string with all five value concatenated. I suspect (without trying this - it's late here and I don't know how this model is using the values to test it appropriately anyway) that just using:

    "20'b00000100000000000000","20'b00001000000000000000","20'b00010000000000000000","20'b00100000000000000000","20'b01000000000000000000"

    would do the job though (i.e. with quotes around each value, and commas between them).

    Andrew

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  • wangyunxin
    wangyunxin over 1 year ago in reply to Andrew Beckett

    Dear  Andrew
     I have try you said  using:

    "20'b00000100000000000000","20'b00001000000000000000","20'b00010000000000000000","20'b00100000000000000000","20'b01000000000000000000"
      Although the simulator is divided into 5 simulations based on these different ki values, their simulation results are all the same. I suspect that the ki value has not been changed successfully.

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  • ShawnLogan
    ShawnLogan over 1 year ago in reply to wangyunxin

    Dear wangyunxin,

    First of all, thank you Andrew for correcting my response! You are correct, I should have written:

    strcat("20'b00000100000000000000" "," "20'b00001000000000000000" "," "20'b00010000000000000000"  ","  "20'b00100000000000000000"  ","  "20'b01000000000000000000")

    However, based on your recent trial wangyunxin, might I suggest you change your verilog-A block to use a decimal input ki in lieu of the binary string? This will avoid this issue as you can set ki to the decimal equivalents of your 20 bit word. I am not sure if this is feasible, but thought I might at least suggest it to avoid the issue.

    Shawn

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  • Andrew Beckett
    Andrew Beckett over 1 year ago in reply to ShawnLogan
    ShawnLogan said:
    strcat("20'b00000100000000000000" "," "20'b00001000000000000000" "," "20'b00010000000000000000"  ","  "20'b00100000000000000000"  ","  "20'b01000000000000000000")

    That won't work either. You've now got a single string value (not a sweep) just with embedded commas in the string. It won't see this as a sweep... (as wangyunxin said, they have got the sweep working anyway - it's just not varying anything).

    ShawnLogan said:
    might I suggest you change your verilog-A block to use a decimal input ki in lieu of the binary string?

    It's not a Verilog-A block by the looks of things. I think it's a Verilog (digital) view since the CDF filter on the edit properties form says "functional". CDF parameters are not normally passed to pure Verilog views without some extra work - see How to pass CDF parameters of an instance to its view when used as External HDL in AMS UNL (there's a link within that article too). Note that I don't have the time to build a test case to try this out - but you might want to look at the instance line in the netlist generated by ADE to see if it's actually passing "ki" to the instance of the block - if not, you'll need to try out the suggestions in the article I linked it.

    My guess is that 

    Andrew

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