VerilogA blind to DC sweep analysis

Use @(above()) rather than @(cross()) - this works even with DC, whereas @(cross) requires at least one timestep. A fairly small rewrite of your model - this works (I think):

`include "disciplines.vams"

module ct_comp(inp, inm, outp, outm, vdd, vss);
input inp, inm;
output outp, outm;
inout vdd, vss;
electrical inp, inm, outp, outm, vdd, vss;

real Vop, Vom;

analog begin

  @ (above( V(inp) - V(inm)));
  @ (cross( V(inp) - V(inm)));

  if(V(inp) > V(inm)) begin
    Vop = V(vdd);
    Vom = V(vss);
  end
  else begin
    Vop = V(vss);
    Vom = V(vdd);
  end

  V(outp) <+ transition(Vop, 10p, 10p, 10p);
  V(outm) <+ transition(Vom, 10p, 10p, 10p);
end
endmodule

I can confirm it works, however I am surprised, shouldn't the IF statements be contained within the above and cross statements to be executed when the related event triggers?

I tried further to use this approach in a verilogA block which should convert a binary input to its decimal representation. Below is the code, where I added the above condition on update signal on both directions to ensure regardless its state the code will be evaluated at any DC analysis, but in this case it does not seem to work:

`include "constants.vams"
`include "disciplines.vams"

module bin2dec_conv(vss, vdd, vref, update, in, out);

inout vss, vdd;
input vref, update;
input [19:0] in;
output out;

electrical vss, vdd;
electrical vref, update;
electrical [19:0] in;
electrical out;

parameter integer Nbits_used = 10;
parameter integer is_signed = 1;

real vtrans, vref_r;
real out_r = 0;
real weight[19:0];
genvar i;

analog begin

vth = V(vdd,vss)/2;
vref_r = V(vref);

@(above(V(update)-vth) or above(-V(update)+vth));

if(!is_signed) begin

@(initial_step or above(V(update)-vth) or above(-V(update)+vth)) begin

out_r=0;
for(i=Nbits_used-1; i>=0; i=i-1) begin

weight[i] = V(in[i])>vth? 1.0/2.0**(Nbits_used-i) : 0.0;
out_r = out_r+weight[i]*vref_r;

end

end

end else begin

@(initial_step or above(V(update)-vth) or above(-V(update)+vth)) begin

out_r=0;
for(i=Nbits_used-1; i>=0; i=i-1) begin

if(i==Nbits_used) begin

weight[i] = V(in[i])>vth ? -1.0/2.0**(Nbits_used-i) : 0.0;

end else begin

weight[i] = V(in[i])>vth? 1.0/2.0**(Nbits_used-i) : 0.0;

end
out_r = out_r+weight[i]*vref_r;

end

end

end

V(out)<+transition(out_r, 0, 10p, 10p);

end

endmodule

NewScreenName said:

I can confirm it works, however I am surprised, shouldn't the IF statements be contained within the above and cross statements to be executed when the related event triggers?

In the case of the comparator, it's fine. That's because the @cross/@above without any body simply ensures there is a timepoint close to the threshold crossing; the output is determined directly by the state of the input at all times, so the if can be evaluated at every time step.

With your bin2dec Verilog-A code above, the update pin seems to be used as a clock to determine when the input should be sampled - so it doesn't make sense to use the same approach. I'm not sure what your bold line is supposed to be doing (it has a different threshold than the other above statements).

I'd have to put together an example netlist to try this out and debug it - no time for that today, sorry (will be a few days most likely before I have some spare time to experiment). The lack of indentation makes it hard to reason about too, but I can fix that when I test it.

Andrew

Andrew Beckett said:

With your bin2dec Verilog-A code above, the update pin seems to be used as a clock to determine when the input should be sampled - so it doesn't make sense to use the same approach. I'm not sure what your bold line is supposed to be doing (it has a different threshold than the other above statements).

Sorry the different threshold was a typo leftover from a modification, I have now fixed it, it is consistently the same threshold and the  goal of it was to force a time point in DC analysis as you suggested for the comparator case. The above statement, in my intent, should always trigger as it checks for V(update) to be above or below vth, one of these two conditions will always be satisfied in DC.

I have also put some indentation, however how can I get automatic indentation for pieces of code in this forum? For this I had to manually indent what I copied from my verilogA model, as the copy&paste doesn't seem to retain indentation from the original code. The format->formats->inline->code formatting option just gives a different font, rather than taking care of identation.

Andrew Beckett said:

will be a few days most likely before I have some spare time to experiment

Sure, even later in time I would greatly appreciate your help here

Best regards

Dear NewScreenName,

NewScreenName said:

I have also put some indentation, however how can I get automatic indentation for pieces of code in this forum? For this I had to manually indent what I copied from my verilogA model, as the copy&paste doesn't seem to retain indentation from the original code. The format->formats->inline->code formatting option just gives a different font, rather than taking care of identation.

Please allow me provide a comment or two (or try to!) to address the easy part of your question quoted above. The degree to which the Forum response dialog box copy and paste functionality preserves tabs or spaces is browser dependent. If I use the Firefox browser, copy and pasting text between a document containing tabs or spaces is preserved when past into the browser Forum reply post window. If I use the Safari browser, the pasting operation does not preserve any tabs or multiple spaces:

However, if you save the content with multiple spaces or tabs into a text files and then upload the text file, the tabs or multiple spaces should be preserved. In this case, I am writing into the Safari browser and uploaded the text file contaning the example code snippet shown above.

Shawn

function(x,y)
{
if (x > y)
	printf("X is greater than Y\n");
else
	printf("X is not greater than y...sorry!\n");
}

Dear NewScreenName,

NewScreenName said:

I have also put some indentation, however how can I get automatic indentation for pieces of code in this forum? For this I had to manually indent what I copied from my verilogA model, as the copy&paste doesn't seem to retain indentation from the original code. The format->formats->inline->code formatting option just gives a different font, rather than taking care of identation.

Please allow me provide a comment or two (or try to!) to address the easy part of your question quoted above. The degree to which the Forum response dialog box copy and paste functionality preserves tabs or spaces is browser dependent. If I use the Firefox browser, copy and pasting text between a document containing tabs or spaces is preserved when past into the browser Forum reply post window. If I use the Safari browser, the pasting operation does not preserve any tabs or multiple spaces:

However, if you save the content with multiple spaces or tabs into a text files and then upload the text file, the tabs or multiple spaces should be preserved. In this case, I am writing into the Safari browser and uploaded the text file contaning the example code snippet shown above.

Shawn

function(x,y)
{
if (x > y)
	printf("X is greater than Y\n");
else
	printf("X is not greater than y...sorry!\n");
}