Compile and elaborate problem with VerilogA blocks in AMS simulation

Hello,

 I´m working on a mixed signal circuit with several blocks in Verilog and others in VerilogA, and there are some problem when running the AMS simulator.

The first ones are compile problem of VerilogA module, while compiling, some blocks would fail. There are errors called MTOCTX, in which warn about some internal nodes defined as real or integer data. The error detail says "Identifier has conflicting contexts. A given object can not be owned ( write access ) by both domains (digital & analog)". This information kind of confuses me cause the internal nodes though be output, the output wire is only be the input of Verilog block and can not be written by Verilog part.

And the second issue is after ignoring all warning verilogA module, the compile success, however, here comes a elaborate problem calling "No connection module found: Need an input port of discrete discipline logic, and an output of continuous displine electrical". All the errors happens ar the outputs of Verilog module.

Is there any solution to run the simulation properly?

Thank you.