Deepprobe within systemverilog hierarchy

clearly I have tried to create a deepprobe defining the net within the systemverilog model itself, but that does not work, it appears as if the net connected to the pin of the deepprobe instance was not saved, although it is saved in the ADE assembler outputs setup tab, and the internal net in the systemverilog model is saved as well, I can successfully plot it reaching it via results browser

The deepprobe only works for electrical signals (or least continuous signals) because it's implemented as an out-of-module reference to an analog node, using an iprobe (a zero voltage source, essentially) within the spectre engine.

What are you hoping to do with this deepprobe? In other words, what were you planning on connecting to the pin end of it?

Regards,

Andrew

My goal is to read the transitions of the probed signal to change dynamically the simulator accuracy, by connecting the dynassert verilogA module described here: https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/57757/dinamycally-changing-errpreset-reltol-based-on-rising-edge-of-a-given-signal#
I also report the code below for easier reading:

`include "disciplines.vams"

module dynassert(trigger);
input trigger;
electrical trigger;

parameter real thresh=1.0;
parameter integer direction=1;
parameter integer crossnum=1;
integer crosscount;
integer assert;

analog 
  @(cross(V(trigger)-thresh,direction)) begin
    crosscount=crosscount+1;
    if(crosscount==crossnum) begin
      $display("Triggered crossing at time ",$abstime);
      assert=1;
    end
  end

endmodule

Furthermore, because this is a periodic signal and I want the simulator accuracy to depend on its state low/high, I was planning to modify the above module into something like this, can this work, or are there better way to do what I'm trying to do?:

`include "disciplines.vams"

module dynassert_h_l(trigger);
input trigger;
electrical trigger;

parameter real thresh=1.0;
integer assert_h, assert_l;

analog 
  @(cross(V(trigger)-thresh)) begin
    if(V(trigger)>thresh) begin
      $display("Triggered rising crossing at time ",$abstime);
      assert_h=1;
      assert_l=0;
    end else begin
      $display("Triggered falling crossing at time",$abstime);
      assert_h=0;
      assert_l=1;
    end
  end

endmodule

Thank you

My goal is to read the transitions of the probed signal to change dynamically the simulator accuracy, by connecting the dynassert verilogA module described here: https://community.cadence.com/cadence_technology_forums/f/mixed-signal-design/57757/dinamycally-changing-errpreset-reltol-based-on-rising-edge-of-a-given-signal#
I also report the code below for easier reading:

`include "disciplines.vams"

module dynassert(trigger);
input trigger;
electrical trigger;

parameter real thresh=1.0;
parameter integer direction=1;
parameter integer crossnum=1;
integer crosscount;
integer assert;

analog 
  @(cross(V(trigger)-thresh,direction)) begin
    crosscount=crosscount+1;
    if(crosscount==crossnum) begin
      $display("Triggered crossing at time ",$abstime);
      assert=1;
    end
  end

endmodule

Furthermore, because this is a periodic signal and I want the simulator accuracy to depend on its state low/high, I was planning to modify the above module into something like this, can this work, or are there better way to do what I'm trying to do?:

`include "disciplines.vams"

module dynassert_h_l(trigger);
input trigger;
electrical trigger;

parameter real thresh=1.0;
integer assert_h, assert_l;

analog 
  @(cross(V(trigger)-thresh)) begin
    if(V(trigger)>thresh) begin
      $display("Triggered rising crossing at time ",$abstime);
      assert_h=1;
      assert_l=0;
    end else begin
      $display("Triggered falling crossing at time",$abstime);
      assert_h=0;
      assert_l=1;
    end
  end

endmodule

Thank you

You might want to look at something like this: Unified VerilogAMS monitor to probe electrical/real/wreal/logic signals in a test bench. I'm not sure it makes sense to do what you are trying because you need some kind of voltage to monitor, and the systemVerilog signal (presumably a real number inside the module) is not a voltage.

You could potentially just use an out-of-module reference to the signal you're trying to monitor too.

Andrew

I have checked the that and created a cell making use of the proposed verilog ams code to instantiate in my testbench the unified monitor, so to connect its output to the dynassert block previously mentioned and control the steppreset.

Now while the probe seems to work fine with analog signals on the rOut output, when I connect it to a logic signal on the lOut pin, it just outputs a Z.

I am not familiar with UVM, therefore I might have missed something, am I supposed to connect something to the input pin of this monitor module? I see that "signal" string is used to determine w_ok and l_ok. 

How I've done it so far was instantiating the monitor in my testbench and passing to it the systemverilog signal I expect it to bring to output on the ppath parameter, while the input pin signals is floating:

And then once that step will work fine, should I still be able to use the dynassert verilogA module as previously described?

I assume a connect module would be automatically placed between the logic output of the monitor and the electrical input of the dynassert.

Thanks

Best regards

It looks as if it should send the signal to the rOut pin of the module, and then I'd expect a R2E connect module to get inserted from that pin (not the logic output though - maybe that was your mistake?).

If that doesn't work (I'm not sure what UVM has to do with anything here - unless you're using UVM?), I would suggest contact customer support. It would be much easier for an application engineer to see this and see how you've connected things up to see what is or isn't working.

Andrew

Hi again,

I have solved the issue with the ams_probe block, so now I can bring to the testbench level internal systemverilog signals. At this point I have a clock and need to set the simulator accuracy according to the level low/high of this clock. I have tried to do it by the following module (same I posted above) and below you can also see the clock connected to the "trigger" input of dynasssert_h_l and how the asserts generated by i_dynassert_level_based_anain have been defined in the transient analysis (ams simulator). By the log file it seems only the first crossing edges of assert_h and assert_l are effectively changing the steppreset. What is wrong and how can I get each crossing to adjust the steppreset?

Thank you.

`include "disciplines.vams"

module dynassert_h_l(trigger);
input trigger;
electrical trigger;

parameter real thresh=1.0;
integer assert_h, assert_l;

analog 
  @(cross(V(trigger)-thresh)) begin
    if(V(trigger)>thresh) begin
      $display("Triggered rising crossing at time ",$abstime);
      assert_h=1;
      assert_l=0;
    end else begin
      $display("Triggered falling crossing at time",$abstime);
      assert_h=0;
      assert_l=1;
    end
  end

endmodule