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Importing mixed-language design (Verilog + VHDL) in Virtuoso AMS

AB_1719514544766 over 1 year ago

Hi,

I am trying to import a digital module in virtuoso for AMS simulation. The hierarchy of the design is shown in the attached diagram. I can import pure VHDL code using File->import->VHDL option and verilog only code using file->import->verilog option but can't find any option to select both Verilog and VHDL submodules for import.

I am new to Mixed-Signal Simulation and Virtuoso so please can anyone help me sort this out? Thanks

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Andrew Beckett over 1 year ago

Why would you need a single option to import both? You can import the Verilog and VHDL separately, and then using the hierarchy editor (i.e. create a "config" view, which you have to do for AMS simulation anyway), you can then pick which views (or "architectures" in VHDL-speak) you'd pick for each cell (or instance or occurrence) in the hierarchy.

You might need (when you are importing) to import in a suitable order - for example, the verilog for module-4, then the VHDL for module-1 and then the top-level verilog and module-2/module-3 - so that you get symbols for each of the blocks that can be specified as a reference library in the appropriate import.

Andrew
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Andrew Beckett over 1 year ago

Why would you need a single option to import both? You can import the Verilog and VHDL separately, and then using the hierarchy editor (i.e. create a "config" view, which you have to do for AMS simulation anyway), you can then pick which views (or "architectures" in VHDL-speak) you'd pick for each cell (or instance or occurrence) in the hierarchy.

You might need (when you are importing) to import in a suitable order - for example, the verilog for module-4, then the VHDL for module-1 and then the top-level verilog and module-2/module-3 - so that you get symbols for each of the blocks that can be specified as a reference library in the appropriate import.

Andrew
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AB_1719514544766 over 1 year ago in reply to Andrew Beckett

Thanks Andrew. I will try to do it that way. Also how can we link submodules in Top Verilog module when our submodule is a Verilog code and also if one of the submodule is a VHDL code? I am only able to link VHDL submodules in a VHDL top module using "use entity work.entity_name(architectural)" syntax for every VHDL submodule.
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Andrew Beckett over 1 year ago in reply to AB_1719514544766

You shouldn't need to do that. Use the config view as I said, and that should cause everything to be bound to the views you want.

Andrew
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