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Interface with systemVerilogText cell

Doronzzz

I'm trying to simulate a toplevel digital logic written in systemVerilog, with array inputs (like input wire [2:0] data_in [15:0]). The problem is that the generated symbol only shows the input port as data_in [2:0]. I'm wondering how can I apply the input data on this cell from a file/other cells in schematic? Also, is it possible to run a systemVerilog testbench with AMS simulator?

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  • AW202410302125

    You might need to flatten the array (e.g., data_in [47:0]) and then parse it manually in the testbench or schematic if that fits your design constraints. For applying input data, try using a readmemh or readmemb file to initialize the array if your simulator supports it.

    Regarding the AMS simulator, running a SystemVerilog testbench can be challenging depending on the simulator you're using. Some AMS simulators are limited in their native support for SystemVerilog testbenches, though you might work around it by co-simulating with a digital simulator that fully supports SystemVerilog.

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  • AW202410302125

    You might need to flatten the array (e.g., data_in [47:0]) and then parse it manually in the testbench or schematic if that fits your design constraints. For applying input data, try using a readmemh or readmemb file to initialize the array if your simulator supports it.

    Regarding the AMS simulator, running a SystemVerilog testbench can be challenging depending on the simulator you're using. Some AMS simulators are limited in their native support for SystemVerilog testbenches, though you might work around it by co-simulating with a digital simulator that fully supports SystemVerilog.

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