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Illegal argument for signal access function [4.3(AMSLRM)]. Verilog AMS error.

BS20240726490

hello exports,

wonder if I can find some help here. 

I want to display the analog signal's voltage at digital clock edge in VerilogAMS code. the compiler keeps telling me this hierarchical signal access is illegal. is there a way to achieve this? the hierarchy path is definitely right as it can compile if I remove "V()" although I don't get the right voltage answer. 

                 ncelab: *E,ILLSARG (..../verilogams/verilog.vams,735|52): Illegal argument for signal access function [4.3(AMSLRM)].

module testbench

   always @(negedge clk ) begin

   ...
      $display("====  %g  ", V(top.sub.leaf) );
   ...
   end

   analog begin 

   ...

   end

endmodule

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  • Hi,

    If $display("==== %g ", top.sub.leaf ) doesn't error out without using V() function, it implies that port/signal 'top.sub.leaf' is not electrical or analog. This also explains why you get an error when you use V(). To debug this, try launching an interactive simulation in Simvision and investigate the signals in the block and their datatype. If you need help in debugging your mixed-signal simulation, please log a case through http://ask.cadence.com.

    Regards,

    Saloni

Reply

  • Hi,

    If $display("==== %g ", top.sub.leaf ) doesn't error out without using V() function, it implies that port/signal 'top.sub.leaf' is not electrical or analog. This also explains why you get an error when you use V(). To debug this, try launching an interactive simulation in Simvision and investigate the signals in the block and their datatype. If you need help in debugging your mixed-signal simulation, please log a case through http://ask.cadence.com.

    Regards,

    Saloni

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