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DC convergence problem with Basic ring amplifier

SC202503236954

I made some basic ring amplifier with Virtuoso, but DC simulation didn't work well.

Below is the schemetic of Bacis Ring amplifier that I made with Virtuoso.

Can anyone tell me what I did wrong with schemetic or simulation?

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  • Since this is a gpdk090-based design, could you please share the input.scs file (I'm not going to re-draw the circuit to test this). You also have given no information about what DC convergence issues you faced (or what you meant by "didn't work well"). From visual inspection, I can say that given the ideal capacitors, and CLK starting low, I'd expect VA, VBP and VBN to be floating during the DC which won't help. It probably would be better to start with the CLK high at time 0 (and hence the DC value would be 0). Also, is VRP correct? It's set to be -300mV (below ground). Perhaps it should have been 300mV below VDD? (not sure, but a voltage below ground is likely to be problematic with a circuit where the bulk is a 0V for the Nmos transistors).

    Andrew

  • in reply to Andrew Beckett

    I change CLK high at time 0 as you told me, and simulation works very well! I'd appreciate your kindness. Thank you!

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