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Noise aware PLL design flow

Hi, I use a collpitts topology for my VCO. While attempting to extract the model of the VCO, I can't give any VSS to my circuit because of this topology. So I get an error when I run PSS/PNOISE. I guess the PLL design flow was designed for LC-VCOs. Is there any work around for the problem? Thanks Sriram

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sriram123 over 14 years ago

Thanks I did as you told and connected VSS to noconnection. The PSS runs for a long time and then returns me this error. I have attached the screenshot. Please help Sriram
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sriram123 over 14 years ago

Thanks I did as you told and connected VSS to noconnection. The PSS runs for a long time and then returns me this error. I have attached the screenshot. Please help Sriram
- PSSfail.png
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