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Noise aware PLL design flow

sriram123
Hi, I use a collpitts topology for my VCO. While attempting to extract the model of the VCO, I can't give any VSS to my circuit because of this topology. So I get an error when I run PSS/PNOISE. I guess the PLL design flow was designed for LC-VCOs. Is there any work around for the problem? Thanks Sriram
Parents

  •  Hir Sriram,

    The error message gave an important clue...you ran out of memory.  Please type in an xterm 

    spectre -h rfmemory 

     like it suggests in the error message.  There are a list of suggestions for you to go through.  If you continue to have difficulty, I suggest contacting Cadence Customer Support.

     

    best regards,

    Tawna

Reply

  •  Hir Sriram,

    The error message gave an important clue...you ran out of memory.  Please type in an xterm 

    spectre -h rfmemory 

     like it suggests in the error message.  There are a list of suggestions for you to go through.  If you continue to have difficulty, I suggest contacting Cadence Customer Support.

     

    best regards,

    Tawna

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