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Jitter cacluation from phase noise??

chadong

Hello everyone,

Maybe many RF & IC designers must be suffer from jitter calculation from phase noise like me.

I read almost all the major documents in google(e.g. Jitter measurements using SpectreRF Application note)

However I can't find any explicit answer or solution about jitter calculation.

Can anybody help me understand the jitter calculation?

My question is simple.

How can I decide the phase noise integration range to calculate jitter?(with selecting noise type as jitter in pnoise)

In many papers, the range was selected 1kHz(10kHz)~10MHz. What's the reason?

In ADI's application note(for ADC), the range was selected 100~2*Fout(i.e. twice of sampling frequency)

Although there are many documents about it, I'm still confused.

Why the phase noise in high frequency is not integrated??

How can I select the low-frequency limit and high-frequency limit for RMS jitter calculation? 

 

Followings are other questions

1) in PSS simulation

-Output harmonics:Number of harmonics

If I am right, the number of harmonics means how many harmonics will be consisted in PSS analysis.

When smaller number used, more noise folded into low frequency. right?? If I'm wrong please point out.

2) in PNOISE simulation

-Output Frequency sweep range

I can't understand this parameter. Even in spectreRF manual, there's no explanation about this.

If I make a free running oscillator 100MHz, what frequency has to be stop frequency? 50MHz? 200MHz?

I selected start frequency to 1Hz

-Sidebands

Maximum sidebands determines the noise folding range

If one sets it 7, noise at higher frequency than 7th sideband will be folded into 1~7 sidebands. right?

 

Thank you for reading

Parents

  • I really appreciate your reply, Frank.

    Your reply was been so helpful to understand the jitter measuring method.

    In conclusion, when I want to know accumulation jitter of free running VCO for driving ADC, I should do following steps.

    1. Pnoise analysis with frequency sweep from 0Hz to f0/2 should be performed.

    2. Maximum sideband of pnoise analysis has to be large enough for accurate result.(at least 10)

    3. Find fc to calculate c. The fc(delta f) is cut off frequency of phase noise(separation point between -30dB/dec and -20dB/dec) 

    4. Caculate c and J. >> J=(c/fo)^0.5

    However, I still have some questions about your above comments, Frank.

    (a) "Only the k-cycle jitter Jc is meaningful for an autonomous circuit"

    >> Cycle jitter means the timing difference between ideal clock and actual output, Cycle-to-cycle jitter means the timing difference between previous cycle and next cycle. Then VCO is autonomous circuit and has no ideal clock as reference. Why the k-cycle jitter Jc is meaningful for an autonomous circuit? From the definition of Jc and Jcc, the meaningful jitter has to be Jcc.  

    (b) "The value of k that you should use for Jc depends on your application. It could for example be the maximum number of consecutive samples that you want to acquire with your ADC."

    >> If all internal blocks of ADC(e.g. clockgen, S/H..) are drived by VCO, k the number of cycle is 1, isn't it?

    (c) "The frequencies fc and fo have nothing to do with integration. They simply specify the range that you should use to determine the parameter c of the equation."

    >> If the frequency fc is 100kHz, selecting delta f 1MHz or 10MHz or any other frequency lower than fo does not affect the result?

     

    Following is another question.

    What I really want to know is the method to calculate jitter by spectreRF.

    For this, I orginized a simulation flow.

    >> pnoise simulation >> direct plot >> main form >> select Jcc >> define number of cycle >> define integration limits from fc to fo/2 >> plot >> Jcc will be calculated.

    Here, the phase noise under fc(Flicker noise area) is not contributed to accumulating jitter and selecting lower limitation of integration range has to do not affect the result.

    Am I right?

Reply

  • I really appreciate your reply, Frank.

    Your reply was been so helpful to understand the jitter measuring method.

    In conclusion, when I want to know accumulation jitter of free running VCO for driving ADC, I should do following steps.

    1. Pnoise analysis with frequency sweep from 0Hz to f0/2 should be performed.

    2. Maximum sideband of pnoise analysis has to be large enough for accurate result.(at least 10)

    3. Find fc to calculate c. The fc(delta f) is cut off frequency of phase noise(separation point between -30dB/dec and -20dB/dec) 

    4. Caculate c and J. >> J=(c/fo)^0.5

    However, I still have some questions about your above comments, Frank.

    (a) "Only the k-cycle jitter Jc is meaningful for an autonomous circuit"

    >> Cycle jitter means the timing difference between ideal clock and actual output, Cycle-to-cycle jitter means the timing difference between previous cycle and next cycle. Then VCO is autonomous circuit and has no ideal clock as reference. Why the k-cycle jitter Jc is meaningful for an autonomous circuit? From the definition of Jc and Jcc, the meaningful jitter has to be Jcc.  

    (b) "The value of k that you should use for Jc depends on your application. It could for example be the maximum number of consecutive samples that you want to acquire with your ADC."

    >> If all internal blocks of ADC(e.g. clockgen, S/H..) are drived by VCO, k the number of cycle is 1, isn't it?

    (c) "The frequencies fc and fo have nothing to do with integration. They simply specify the range that you should use to determine the parameter c of the equation."

    >> If the frequency fc is 100kHz, selecting delta f 1MHz or 10MHz or any other frequency lower than fo does not affect the result?

     

    Following is another question.

    What I really want to know is the method to calculate jitter by spectreRF.

    For this, I orginized a simulation flow.

    >> pnoise simulation >> direct plot >> main form >> select Jcc >> define number of cycle >> define integration limits from fc to fo/2 >> plot >> Jcc will be calculated.

    Here, the phase noise under fc(Flicker noise area) is not contributed to accumulating jitter and selecting lower limitation of integration range has to do not affect the result.

    Am I right?

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