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Syminductor layout problem

peter450

 Hi,

I'm implementing a design that has syminductor.When I'm running LVS I'm getting parameter mismatch

"wu" layout 1.44e-5 schematic -1e-6

But the values of wu for schematic and layout are same in the design.

Parents

  • The last time I used IBM CMOS 130nm it had a similar problem with LVS and extracting symmetric inductors, but with the coil spacing. AFAIK the problem still exists in the current PDK and users are advised to edit the extracted netlist to correct this before moving to postlayout simulation.

Reply

  • The last time I used IBM CMOS 130nm it had a similar problem with LVS and extracting symmetric inductors, but with the coil spacing. AFAIK the problem still exists in the current PDK and users are advised to edit the extracted netlist to correct this before moving to postlayout simulation.

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