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Syminductor layout problem

peter450

 Hi,

I'm implementing a design that has syminductor.When I'm running LVS I'm getting parameter mismatch

"wu" layout 1.44e-5 schematic -1e-6

But the values of wu for schematic and layout are same in the design.

  • Nobody is going to be able to help you unless they know which technology you're using and which specific design kit version you're using. The software version wouldn't go amiss either.

    Then there's a chance somebody might be familiar with the specific problem.

    The name "syminductor" doesn't give much of a clue... (I could guess the foundry, but not which design kit it is for)

    Andrew

  •  I'm using cadence bicmos8hp 130nm technology.

  • Presumably you meant IBM, not Cadence. We're not a foundry and do not produce the design kits for that technology...

    You should also state the version of the design kit you're using and the versions of Cadence tools that you're using (as I said before) if you want to increase the chances of a user of that design kit, or somebody from IBM, answering your question.

    Andrew

  • The last time I used IBM CMOS 130nm it had a similar problem with LVS and extracting symmetric inductors, but with the coil spacing. AFAIK the problem still exists in the current PDK and users are advised to edit the extracted netlist to correct this before moving to postlayout simulation.

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