This happens if you have multiple voltage sources in parallel or multiple inductors in parallel (or voltage sources in parallel with inductors). If you think about it, that makes sense because such a scenario leads to an unsolvable matrix.
So without seeing your exact circuit, that's going to be the problem. There are some unusual cases where behavioural models can misreport this error if you have switch branches in your VerilogA, and that can be worked around with an attribute, but I doubt that's your issue here.
Thank you for your attention and the message. Unfortunately, this system does not appear to let me attach the image of my schematic; as such, I will have to provide you with more details on the circuit topology, as follows:
I am using a symmetrical inductor with a center wire that is the common-mode point. Therefore, there are three terminals involved. The symmetrical inductor also has another terminal that is not the signal terminal, but must be connected to the power supply. With that in mind, I have connected a Psin Port with 25 Ohms source resistance to the common-mode point. I have also connected another Psin Port with 100 Ohms source impedance across the other two terminals of the symmetrical inductor. Additionally, I have connect the two terminals of the symmetrical inductor to two (2) 50-Ohm resistors (i.e., each 50-Ohm resistor is connected between one terminal of the inductor and ground).
Now, when I run the SP analysis, I receive the error described in the subject. As you see, no voltage source or inductor is in parallel. I even inserted 1-Ohm resistor in series with the two Psin ports; however, I received the same result. Please note that this symmetrical inductor is not an ideal inductor; as such, it has parasitic inductance, capacitance, and resistance.
Thank you again for your attention, and I hope you can provide a work-around to this issue.
You can attach pictures - use the Options tab when posting a reply. It would also help to post the precise error message (which indicates the components involved). It's pretty hard to visualize just from your description.
Alternatively if there is information you cannot post in a public forum, you should go to Customer Support (http://support.cadence.com)
Thank you again for your attention. I have attached the screen shot of the schematic for your attention and reference. Unfortunately, this site does not allow uploading more that one (1) screen shot; as such, I will upload the error message screen shot in the next post.