Does capacitor in analoglib have some leak current?

Simulation results are presented below.

It is obvious that V(n2) goes up to 1V because of the input excitation, and then descends with time.

I think capacitor is ideal. So why can't V(n2) stay at 1V? Is the capacitor not ideal? Does the capacitor model have some leakage current? 

Can anyone help me, please? Thanks a lot!

HI xxgenerall,

Have you tried a DC simulation and examined the voltage of node n2? I believe the steady-state voltage across n2 is 0 V - not 1V. The initial voltage of 1 V is due to displacement current and the charge is then re-distributed to set the voltage across the capacitor connected to ground to 0.

 Put another way, if the rise time of the 2 V signal is very long (dv/dt is about 0), the node voltage at n1 will eventually rise to 2V, but the voltage at n2 will never change from 0. 

Shawn 

The reason for this is that there is no DC path from n1 to ground (it's floating at DC), and so the simulator inserts a gmin resistor to ground. Since the default value of gmin is 1e-12 Siemens (1e12 ohms), you then have a 2 second time constant - if you simulate for 2 seconds you'll see it's down to 0.369mV (i.e. 63% of the way there, what you'd expect after a time constant).

In this trivial circuit, you could set the option gmin to 0 (this is generally not a good idea, as gmin conductances are there to aid convergence - having absolutely no path to ground means that there are an infinite number of solutions for the DC operating point, since a floating node could be anything; a high value like 1e12 ohms is not unrealistic in terms of leakage).

Regards,

Andrew.

Hi all, I appreciate your help. Thank you very much. ^_^