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Does capacitor in analoglib have some leak current?

xxgenerall

Hi everyone,

I've simulated a very simple circuit, as follows.

It has a step-up signal as input. And signal "n2" is interesting.

Parents

  • HI xxgenerall,

    Have you tried a DC simulation and examined the voltage of node n2? I believe the steady-state voltage across n2 is 0 V - not 1V. The initial voltage of 1 V is due to displacement current and the charge is then re-distributed to set the voltage across the capacitor connected to ground to 0.

     Put another way, if the rise time of the 2 V signal is very long (dv/dt is about 0), the node voltage at n1 will eventually rise to 2V, but the voltage at n2 will never change from 0. 

     

    Shawn 

Reply

  • HI xxgenerall,

    Have you tried a DC simulation and examined the voltage of node n2? I believe the steady-state voltage across n2 is 0 V - not 1V. The initial voltage of 1 V is due to displacement current and the charge is then re-distributed to set the voltage across the capacitor connected to ground to 0.

     Put another way, if the rise time of the 2 V signal is very long (dv/dt is about 0), the node voltage at n1 will eventually rise to 2V, but the voltage at n2 will never change from 0. 

     

    Shawn 

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