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How to avoid Hidden State in VerilogA model for SpectreRF

RFStuff

 Dear All,

I am a beginner in verilogA .

I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.

My behavioural model is as below:-

 

 

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"
`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);
  inout in,out;
  parameter real vtrans = 0;
  parameter real tdelay = 0 from [0:inf);
  parameter real trise = 1p from (0:inf);
  parameter real tfall = 1p from (0:inf);
  parameter real Gm=-5m;
  electrical in,out;
  real vout_val;
  analog begin
 
         @ (cross(V(in) - vtrans, 1))  vout_val = 1;
         @ (cross(V(in) - vtrans, -1)) vout_val = 0;
 
         I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); 
  end   
endmodule

 

Could anybody please tell how I can avoid the hidden state  (vout_val ) ?

 

Kind Regards,

Parents

  • Hello, I'm also new with  Verilog A. I would like to run a pss in a circuit that has a block with only a veriloga view. It's a D flip-flop double edge. I wrote the veriloga code according to the advice in this post, but I still have a hidden state. 

    Here's the code:

    // Double edge Flip Flop

    `include "constants.vams"

    `include "disciplines.vams"

     

    module DFF_DEDGE(q, clk, d);

     input clk,d;

     output q;

     voltage q, clk, d;

     parameter real tdelay   = 1n from [0:inf),

                    ttransit = 20p from [0:inf),

                    vout_high = 1,

                    vout_low  = 0 from (-inf:vout_high),

                    vth       = 0.5;

     

     integer x;

     analog

     begin

       @(initial_step) x = 0;

     

       @(cross(V(clk) - vth )) x = (V(d) > vth);

     

       V(q)    <+ transition( vout_high*x  + vout_low*!x, tdelay, ttransit );

       

      

     end

    endmodule

     

    If I run a PSS, I got the following error message

     ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'DFF_DEDGE'.  Skipped.

      ... : Hidden state variable: x

     

    How can I modify the code to avoid it?

    Thanks a lot! 

Reply

  • Hello, I'm also new with  Verilog A. I would like to run a pss in a circuit that has a block with only a veriloga view. It's a D flip-flop double edge. I wrote the veriloga code according to the advice in this post, but I still have a hidden state. 

    Here's the code:

    // Double edge Flip Flop

    `include "constants.vams"

    `include "disciplines.vams"

     

    module DFF_DEDGE(q, clk, d);

     input clk,d;

     output q;

     voltage q, clk, d;

     parameter real tdelay   = 1n from [0:inf),

                    ttransit = 20p from [0:inf),

                    vout_high = 1,

                    vout_low  = 0 from (-inf:vout_high),

                    vth       = 0.5;

     

     integer x;

     analog

     begin

       @(initial_step) x = 0;

     

       @(cross(V(clk) - vth )) x = (V(d) > vth);

     

       V(q)    <+ transition( vout_high*x  + vout_low*!x, tdelay, ttransit );

       

      

     end

    endmodule

     

    If I run a PSS, I got the following error message

     ERROR (SPCRTRF-15177): PSS analysis doesn't support behavioral module components with hidden states found in component 'DFF_DEDGE'.  Skipped.

      ... : Hidden state variable: x

     

    How can I modify the code to avoid it?

    Thanks a lot! 

Children
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