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How to avoid Hidden State in VerilogA model for SpectreRF

RFStuff

 Dear All,

I am a beginner in verilogA .

I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.

My behavioural model is as below:-

 

 

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"
`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);
  inout in,out;
  parameter real vtrans = 0;
  parameter real tdelay = 0 from [0:inf);
  parameter real trise = 1p from (0:inf);
  parameter real tfall = 1p from (0:inf);
  parameter real Gm=-5m;
  electrical in,out;
  real vout_val;
  analog begin
 
         @ (cross(V(in) - vtrans, 1))  vout_val = 1;
         @ (cross(V(in) - vtrans, -1)) vout_val = 0;
 
         I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); 
  end   
endmodule

 

Could anybody please tell how I can avoid the hidden state  (vout_val ) ?

 

Kind Regards,

Parents

  • Hi Andrew,

     I will like to know while this Normalised LMS algorithm could not be supported in PSS analysis due to the hidden state variable "WtsReg".

    Can you please help proffer solution or suggestion to the code in verilogA.

    // VerilogA for IM2_Cancellation, LMS, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module LMS(clk,Inp_Sig,Error, Wts);

    input clk, Error,Inp_Sig;
    electrical clk, Error,Inp_Sig;
    output Wts;
    electrical Wts;

    parameter real mu=0.2 ; //varies between 0 to 2

    integer  vth;
    integer Clk;
    real ErrorReg;
    real WtsReg;
    integer Vin;
    real Quot;

    analog begin
            Clk = (V(clk)> 0.5)? 1:0;

            @(initial_step)
            begin

                    WtsReg = 0;
                    V(Wts) <+ 0;
            end

            if (V(Inp_Sig)) begin

                    ErrorReg =  V(Error);
                    V(Wts) <+ WtsReg;

            end

            @ (cross(Clk - 0.5, +1)) // rising edge of clock signal
            begin
                    ErrorReg =  V(Error);
                    Quot = V(Inp_Sig)/(V(Inp_Sig)*V(Inp_Sig));

                    WtsReg = WtsReg + mu * ErrorReg * Quot;

            end
    end
    endmodule

Reply

  • Hi Andrew,

     I will like to know while this Normalised LMS algorithm could not be supported in PSS analysis due to the hidden state variable "WtsReg".

    Can you please help proffer solution or suggestion to the code in verilogA.

    // VerilogA for IM2_Cancellation, LMS, veriloga

    `include "constants.vams"
    `include "disciplines.vams"

    module LMS(clk,Inp_Sig,Error, Wts);

    input clk, Error,Inp_Sig;
    electrical clk, Error,Inp_Sig;
    output Wts;
    electrical Wts;

    parameter real mu=0.2 ; //varies between 0 to 2

    integer  vth;
    integer Clk;
    real ErrorReg;
    real WtsReg;
    integer Vin;
    real Quot;

    analog begin
            Clk = (V(clk)> 0.5)? 1:0;

            @(initial_step)
            begin

                    WtsReg = 0;
                    V(Wts) <+ 0;
            end

            if (V(Inp_Sig)) begin

                    ErrorReg =  V(Error);
                    V(Wts) <+ WtsReg;

            end

            @ (cross(Clk - 0.5, +1)) // rising edge of clock signal
            begin
                    ErrorReg =  V(Error);
                    Quot = V(Inp_Sig)/(V(Inp_Sig)*V(Inp_Sig));

                    WtsReg = WtsReg + mu * ErrorReg * Quot;

            end
    end
    endmodule

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