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How to avoid Hidden State in VerilogA model for SpectreRF

RFStuff

 Dear All,

I am a beginner in verilogA .

I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.

My behavioural model is as below:-

 

 

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"
`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);
  inout in,out;
  parameter real vtrans = 0;
  parameter real tdelay = 0 from [0:inf);
  parameter real trise = 1p from (0:inf);
  parameter real tfall = 1p from (0:inf);
  parameter real Gm=-5m;
  electrical in,out;
  real vout_val;
  analog begin
 
         @ (cross(V(in) - vtrans, 1))  vout_val = 1;
         @ (cross(V(in) - vtrans, -1)) vout_val = 0;
 
         I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall); 
  end   
endmodule

 

Could anybody please tell how I can avoid the hidden state  (vout_val ) ?

 

Kind Regards,

Parents

  • Did you read the http://www.designers-guide.org/Analysis/hidden-state.pdf paper I pointed at earlier in this thread? The problem is that you are relying on sampling the signal at the clock edge into the variable WtsReg which is then a hidden state variable. You need to employ one of the strategies discussed in that paper so that this state is represented as an electrical node rather than a variable; variables have to be updated on every iteration.

    It's also not a good idea to have the contribution statement (the V(Wts)<+WtsReg;) inside a conditional statement - in fact I'm not sure that's really doing anything useful (so remove the surrounding if() statement).

    This thread seems to have become a bit of a dumping ground for questions on hidden state; the forum guidelines ask forum users not to post on the end of old threads to avoid muddying the answers and making it harder for people to find specific answers to specific questions.

    Kind Regards,

    Andrew.

Reply

  • Did you read the http://www.designers-guide.org/Analysis/hidden-state.pdf paper I pointed at earlier in this thread? The problem is that you are relying on sampling the signal at the clock edge into the variable WtsReg which is then a hidden state variable. You need to employ one of the strategies discussed in that paper so that this state is represented as an electrical node rather than a variable; variables have to be updated on every iteration.

    It's also not a good idea to have the contribution statement (the V(Wts)<+WtsReg;) inside a conditional statement - in fact I'm not sure that's really doing anything useful (so remove the surrounding if() statement).

    This thread seems to have become a bit of a dumping ground for questions on hidden state; the forum guidelines ask forum users not to post on the end of old threads to avoid muddying the answers and making it harder for people to find specific answers to specific questions.

    Kind Regards,

    Andrew.

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