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[Help] About the simulation of Wien-bridge OSC.

xxgenerall

The Wien-bridge OSC is as below.

R=1K Ohms, C=1uF, so f=1/(2*pi*R*C)=159Hz. And the BW of the operational amplifier is 9KHz. Theoretically, the OSC outputs a sine wave.

However, the OSC keeps a common voltage, which is another steady state.

Is there something wrong with my simulation setup? Can you help me, please? Thanks a lot.

Parents

  • And here's the schematic (I've included the input.scs so you can see the component values):

    // Generated for: spectre
    // Generated on: Apr 14 23:38:46 2014
    // Design library name: mylib
    // Design cell name: wienBridgeOsc
    // Design view name: schematic
    simulator lang=spectre
    global 0

    // Library name: mylib
    // Cell name: wienBridgeOsc
    // View name: schematic
    I0 (op vcom net3 net4 vdd 0) opamp gain=100000 freq_unitygain=1M
    R3 (net3 vcom) resistor r=1K
    R2 (op net10) resistor r=1K
    R1 (op net4) resistor r=2.5K
    R0 (net4 vcom) resistor r=1K
    C1 (net3 vcom) capacitor c=1u
    C0 (net10 net3) capacitor c=1u
    E0 (vcom 0 vdd 0) vcvs gain=0.5
    V0 (vdd 0) vsource type=pulse val0=0 val1=3.3 delay=1n rise=10n
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    dcOp dc force=all write="spectre.dc" maxiters=150 maxsteps=10000 \
        annotate=status
    dcOpInfo info what=oppoint where=rawfile
    tran tran stop=100m maxstep=0.1m write="spectre.ic" \
        writefinal="spectre.fc" annotate=status maxiters=5
    finalTimeOP info what=oppoint where=rawfile
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    saveOptions options save=allpub
    ahdl_include "/export/home/apps/IC615_isr/tools/dfII/samples/artist/ahdlLib/opamp/veriloga/veriloga.va"

    Regards,

    Andrew.

Reply

  • And here's the schematic (I've included the input.scs so you can see the component values):

    // Generated for: spectre
    // Generated on: Apr 14 23:38:46 2014
    // Design library name: mylib
    // Design cell name: wienBridgeOsc
    // Design view name: schematic
    simulator lang=spectre
    global 0

    // Library name: mylib
    // Cell name: wienBridgeOsc
    // View name: schematic
    I0 (op vcom net3 net4 vdd 0) opamp gain=100000 freq_unitygain=1M
    R3 (net3 vcom) resistor r=1K
    R2 (op net10) resistor r=1K
    R1 (op net4) resistor r=2.5K
    R0 (net4 vcom) resistor r=1K
    C1 (net3 vcom) capacitor c=1u
    C0 (net10 net3) capacitor c=1u
    E0 (vcom 0 vdd 0) vcvs gain=0.5
    V0 (vdd 0) vsource type=pulse val0=0 val1=3.3 delay=1n rise=10n
    simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
        tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
        digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
        checklimitdest=psf
    dcOp dc force=all write="spectre.dc" maxiters=150 maxsteps=10000 \
        annotate=status
    dcOpInfo info what=oppoint where=rawfile
    tran tran stop=100m maxstep=0.1m write="spectre.ic" \
        writefinal="spectre.fc" annotate=status maxiters=5
    finalTimeOP info what=oppoint where=rawfile
    modelParameter info what=models where=rawfile
    element info what=inst where=rawfile
    outputParameter info what=output where=rawfile
    designParamVals info what=parameters where=rawfile
    primitives info what=primitives where=rawfile
    subckts info what=subckts  where=rawfile
    saveOptions options save=allpub
    ahdl_include "/export/home/apps/IC615_isr/tools/dfII/samples/artist/ahdlLib/opamp/veriloga/veriloga.va"

    Regards,

    Andrew.

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