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Transient Output Log

Hello all,

I am a newbie to cadence and want to understand output log of cadence well. I attached an image of output log as it appears during transient analysis. Is it normal to get such a message ? Can you please explain how to verify if my circuits violates any of the above conditions ?

Regards.

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Sai Goutham over 11 years ago

Thank you for your answer Mr. Beckett. I see "Vbs-Vds getting forward biased " warning in my output log for transient simulations. Is this a problem to my circuit ? I have attached an image showing it.

Thanks.
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Sai Goutham over 11 years ago

Thank you for your answer Mr. Beckett. I see "Vbs-Vds getting forward biased " warning in my output log for transient simulations. Is this a problem to my circuit ? I have attached an image showing it.

Thanks.
- Capture.PNG
- View
- Hide
Cancel
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