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How to use MOSFET as a switch to introduce a capacitor into a LC tank in VCO?

Alex Liao

Hi guys,

In my VCO design, if I introduce a fixed capacitance, Cap_fix into the C tank, it works fine and give me the target frequency I want. If I disconnect this path (in parallel with the total C) to disable the introduction of this Cap_fix, it gives me higher frequency and it is reasonable as it follows：
w = 1/sqrt(C*L).

But if I want to implement this on/off feature using a MOSFET it does not work.
It always generates strange frequency. I was observing the target frequency through Cadence DFT function of the output in the ADE panel.

Working as a switch, I treated the D and S ends as the switch's two ends. I biased the MOSEFT in triode (ohmic) region, which means,
give me a small Ron (1/gds) when it is on and a infinite large Ron when it is off. For MOSFET size, I tried several combinations, still not working. Either the harmonic signal's strength is high or sometimes output some unreasonable DFT waveform.

Is it such tricky on just using a triode region MOSFET as a simple on/off switch in RF circuit? Or was I implementing the switch using MOSFET in a wrong way? or any tips on bias or sizing this MOSFET? Shouldn't be the reason of my core design as it works fine by simply connecting/disconnect a regular capacitor into the LC tank.

Any reply is appreciated!
Thanks,
Alex

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  • ShawnLogan

    Dear Alex,

    > Is there any wrong for the ideal case's output and/ or the design?

    I took a look at your basic VCO circuit. I do not know if your inductors are ideal or have a finite Q. It also appears as if there are no parasitic layout capacitances nor resistances. Each of these will lower your negative resistance in magnitude as well as reduce oscillator steady-state amplitude. They will also impact the oscillation frequency. If these are not included, your waveform amplitude may be unrealistically large - which could be why you are observing the large voltage swing.

    As for your switches, I might suggest a different MOS switch and capacitor topology to assist in the control of your MOS switches. Since your VCO is basically a differential circuit, you can take advantage of that fact by splitting each added capacitor Cb0, Cb1, Cb2, and Cb3 into sets of 2 series capacitors. For example, replace Cb0 with two capacitors Cb0a and Cb0b where Cb0a = Cb0b = 2*Cb0. One node of Cb0a connects to node +V/2, and one node of Cb0b connects to node -V/2. Place the MOS switch for Cb0a and Cb0b between the two capacitors. In this fashion, the drain and source of the MOS device is at an AC virtual ground since the oscillator is differential. The range of DC values of the MOS drain and source will be less than in your present topology. As a result, setting the gate voltage to assure the switch is on or off may be easier. In the topology you have shown, one side of each switch sees the full swing of one side of the differential VCO output. As a result, it will be more difficult to provide robust MOS switch control.

    I hope this makes sense Alex.

    Shawn

Reply
  • ShawnLogan

    Dear Alex,

    > Is there any wrong for the ideal case's output and/ or the design?

    I took a look at your basic VCO circuit. I do not know if your inductors are ideal or have a finite Q. It also appears as if there are no parasitic layout capacitances nor resistances. Each of these will lower your negative resistance in magnitude as well as reduce oscillator steady-state amplitude. They will also impact the oscillation frequency. If these are not included, your waveform amplitude may be unrealistically large - which could be why you are observing the large voltage swing.

    As for your switches, I might suggest a different MOS switch and capacitor topology to assist in the control of your MOS switches. Since your VCO is basically a differential circuit, you can take advantage of that fact by splitting each added capacitor Cb0, Cb1, Cb2, and Cb3 into sets of 2 series capacitors. For example, replace Cb0 with two capacitors Cb0a and Cb0b where Cb0a = Cb0b = 2*Cb0. One node of Cb0a connects to node +V/2, and one node of Cb0b connects to node -V/2. Place the MOS switch for Cb0a and Cb0b between the two capacitors. In this fashion, the drain and source of the MOS device is at an AC virtual ground since the oscillator is differential. The range of DC values of the MOS drain and source will be less than in your present topology. As a result, setting the gate voltage to assure the switch is on or off may be easier. In the topology you have shown, one side of each switch sees the full swing of one side of the differential VCO output. As a result, it will be more difficult to provide robust MOS switch control.

    I hope this makes sense Alex.

    Shawn

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