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How to use MOSFET as a switch to introduce a capacitor into a LC tank in VCO?

Alex Liao

Hi guys,

In my VCO design, if I introduce a fixed capacitance, Cap_fix into the C tank, it works fine and give me the target frequency I want. If I disconnect this path (in parallel with the total C) to disable the introduction of this Cap_fix, it gives me higher frequency and it is reasonable as it follows：
w = 1/sqrt(C*L).

But if I want to implement this on/off feature using a MOSFET it does not work.
It always generates strange frequency. I was observing the target frequency through Cadence DFT function of the output in the ADE panel.

Working as a switch, I treated the D and S ends as the switch's two ends. I biased the MOSEFT in triode (ohmic) region, which means,
give me a small Ron (1/gds) when it is on and a infinite large Ron when it is off. For MOSFET size, I tried several combinations, still not working. Either the harmonic signal's strength is high or sometimes output some unreasonable DFT waveform.

Is it such tricky on just using a triode region MOSFET as a simple on/off switch in RF circuit? Or was I implementing the switch using MOSFET in a wrong way? or any tips on bias or sizing this MOSFET? Shouldn't be the reason of my core design as it works fine by simply connecting/disconnect a regular capacitor into the LC tank.

Any reply is appreciated!
Thanks,
Alex

Parents
  • Alex Liao

    Hello Shawn,

    smlogan said:
    I took a look at your basic VCO circuit. I do not know if your inductors are ideal or have a finite Q. It also appears as if there are no parasitic layout capacitances nor resistances. Each of these will lower your negative resistance in magnitude as well as reduce oscillator steady-state amplitude. They will also impact the oscillation frequency. If these are not included, your waveform amplitude may be unrealistically large - which could be why you are observing the large voltage swing.

    The device model of the inductors are adopted from normal ones in which I did not set Res (0 by default), so I would think of Q to be relatively high.

    Also as I only performed the pre-layout simulation so no parasitics are included. From what you said, if I manual introduce some Resistance for the inductors and some paracitics (maybe anywhere in the circuit), the output swing should be decreased. Is that right? It looks I make everything too ideal causing the large swing. Is there any specific nodes, once parasitics appear, that make the performance very parasitic sensitive?

    smlogan said:
    The range of DC values of the MOS drain and source will be less than in your present topology. As a result, setting the gate voltage to assure the switch is on or off may be easier.

    Thanks for you nice structure, I did see that the resultant structure results in a better performance. That is, getting close to the ideal case regardless of the fact of large output swing. Thanks!!!

    But I want to try one more thing to make the current structure more usable. That is, I want to measure how much impedance introduced since I have replaced the ideal switches with  MOSFET switches. (Like measure the C_equivalent between Voutp and Voutn). The basic ideas is to do a AC analysis and measure the Voltage/Current. And then acquire the imaginary part of the impedance. I am presenting the adopted equations I tried in the output setup or in the ADE calculator. None of them work.

    1. imag(value((VF("/net1")-VF("/net2"))/IF("/I0/M1/G") 1e3 ))

    2. imag(value(VF("/net1")-VF("/net2") 1e3) /value(IF("/I0/M1/G") 1e3 ) )

    Did I make some mistake on calculating the impedance?

    Thanks,

    Alex

Reply
  • Alex Liao

    Hello Shawn,

    smlogan said:
    I took a look at your basic VCO circuit. I do not know if your inductors are ideal or have a finite Q. It also appears as if there are no parasitic layout capacitances nor resistances. Each of these will lower your negative resistance in magnitude as well as reduce oscillator steady-state amplitude. They will also impact the oscillation frequency. If these are not included, your waveform amplitude may be unrealistically large - which could be why you are observing the large voltage swing.

    The device model of the inductors are adopted from normal ones in which I did not set Res (0 by default), so I would think of Q to be relatively high.

    Also as I only performed the pre-layout simulation so no parasitics are included. From what you said, if I manual introduce some Resistance for the inductors and some paracitics (maybe anywhere in the circuit), the output swing should be decreased. Is that right? It looks I make everything too ideal causing the large swing. Is there any specific nodes, once parasitics appear, that make the performance very parasitic sensitive?

    smlogan said:
    The range of DC values of the MOS drain and source will be less than in your present topology. As a result, setting the gate voltage to assure the switch is on or off may be easier.

    Thanks for you nice structure, I did see that the resultant structure results in a better performance. That is, getting close to the ideal case regardless of the fact of large output swing. Thanks!!!

    But I want to try one more thing to make the current structure more usable. That is, I want to measure how much impedance introduced since I have replaced the ideal switches with  MOSFET switches. (Like measure the C_equivalent between Voutp and Voutn). The basic ideas is to do a AC analysis and measure the Voltage/Current. And then acquire the imaginary part of the impedance. I am presenting the adopted equations I tried in the output setup or in the ADE calculator. None of them work.

    1. imag(value((VF("/net1")-VF("/net2"))/IF("/I0/M1/G") 1e3 ))

    2. imag(value(VF("/net1")-VF("/net2") 1e3) /value(IF("/I0/M1/G") 1e3 ) )

    Did I make some mistake on calculating the impedance?

    Thanks,

    Alex

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