I am designing a PLL and I want to plot the frequency response of it. I have chosen to plot it using STB analysis in cadence. So what I have done is I did break the feedback loop from frequency divider to PFD and inserted a probe. I have the figure which shows how I have given the inputs. But the output that I get is as given below which is incorrect. My question is, Is it the correct way to plot the frequency response of pll? If it is then where am I going wrong? What should I modify for a proper output?
This won't work. The stb analysis is a small signal analysis around a particular bias point (operating point). Almost certainly your PLL doesn't have a small signal loop gain - so this can't work.
You might want to look at this PLL Verification Workshop (one of our Rapid Adoption Kits) to help guide you with approaches for PLL verification.