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Phase Noise Setup doesn't work in port/vsource

VIP of NH

I'm simply simulating pss and pnoise for a port/vsource, with added phase noise "freq, noise(dBc)" pairs.

In my testbench, there's only the vsource and it's labelled output, and gnd. 

In ade, I setup pss output as voltage between vsource positive and vsource negative(gnd), no input.

But the simulation result in Direct Plot -> pnoise -> Phase Noise gives me a straight line with same value for all frequencies.

Then it means either the added Phase Noise pairs don't work, or there's sth wrong with my simulation.

Could you please tell me why?

Thank you very much.

Here's my testbench and vsource setup (when I use port, the setup is almost the same, only with a 50 Ohm impedance for the port)

Here's the ade setup for pss and pnoise:

Here's the simulation result plot of phase noise:

 

Parents

  • Thanks a lot Andrew! I'm using Virtuoso 6.1.6 and MMSIM/spectre 13.1

    Now I found a very weird thing:

    Since I'm designing and simulating a PLL now, I was using an ideal VCO (verilog-A), and pss can converge and give result.

    But when I changed it to be transistor-level real VCO, even though pss can converge, I found the pss gives wrong result:

    1. "Direct Plot -> pss -> voltage -> time" for VCO output node is not oscillating (red plot below), the DC value of it indeed should be 0.5V;

    2. I have confirmed with transient simulation that it can oscillate, and the whole PLL loop can lock;

    3. "Direct Plot -> tstab -> PSS Transient V" for VCO output node is correct and consistent with transient simulation result. (You can see the DC level is 0.5V, and it has a start up time around 2.5ns)

    The weird thing is that the pss can even converge while @20ns the PLL loop is not locked yet (can be verified in transient.)

    And I guess the pss result previously with ideal VCO is also wrong.

    My PLL is a 100MHz input, 40.5GHz output one. I'm using the previously mentioned 100MHz sine PORT as input.

    Here's my setup for pss:

    My questions is:

    1. Why pss/voltage/time for VCO output is like that? Is there anything wrong with my setup? Why it's not consistent with transient sim result?

    2. Since I give a tstab in pss setup, when plotting pss/voltage/time, should the x-axis be from tstab(or the stable moment when convergence happens) to tstab+beat_period, instead of 0 to beat_period?

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  • Thanks a lot Andrew! I'm using Virtuoso 6.1.6 and MMSIM/spectre 13.1

    Now I found a very weird thing:

    Since I'm designing and simulating a PLL now, I was using an ideal VCO (verilog-A), and pss can converge and give result.

    But when I changed it to be transistor-level real VCO, even though pss can converge, I found the pss gives wrong result:

    1. "Direct Plot -> pss -> voltage -> time" for VCO output node is not oscillating (red plot below), the DC value of it indeed should be 0.5V;

    2. I have confirmed with transient simulation that it can oscillate, and the whole PLL loop can lock;

    3. "Direct Plot -> tstab -> PSS Transient V" for VCO output node is correct and consistent with transient simulation result. (You can see the DC level is 0.5V, and it has a start up time around 2.5ns)

    The weird thing is that the pss can even converge while @20ns the PLL loop is not locked yet (can be verified in transient.)

    And I guess the pss result previously with ideal VCO is also wrong.

    My PLL is a 100MHz input, 40.5GHz output one. I'm using the previously mentioned 100MHz sine PORT as input.

    Here's my setup for pss:

    My questions is:

    1. Why pss/voltage/time for VCO output is like that? Is there anything wrong with my setup? Why it's not consistent with transient sim result?

    2. Since I give a tstab in pss setup, when plotting pss/voltage/time, should the x-axis be from tstab(or the stable moment when convergence happens) to tstab+beat_period, instead of 0 to beat_period?

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