high frequency D flip flop for phase detector

I'm not aware of there being any specific examples for something as simple as this. I cannot see any good reason why you should have any difficulty simulating such a circuit. It might have problems with reaching a metastable state, but I don't know what you mean by "goes bad". Perhaps you should talk to your supervisor?

Regards,

Andrew.

Dear yefj,

I have simulated this phase detector topology on many occasions in spectre successfully. However, I have no idea why you would use this at a frequency of 5 GHz. This is probably the reason you are having problems. For a 5 GHz reference clock, your period is 200 ps. Therefore, the propagation delay of your DFF combined with the AND gate and reset function of the DFF must be far less than 200 ps. Further, I would expect the dead zone of a 5 GHz version of this phase detector will be significant given the limited propagation delay time. If you are trying to use this in a phase-locked loop with a 5 GHz VCO, it is far more common to use a feedback divider to reduce the frequency of your VCO to that of a reasonable reference clock frequency of, say, less than 200 MHz. I might suggest you try simulating your phase detector with input clocks at a much lower frequency to establish its functionality.

Shawn

Hello Shawn, i tried  to implement a 250MHZ TSPC FLIP FLOP, there are two stages Q_hold(the inner storage of data and Q the output of the FLIP FLOP.

First i defined in initial conditions both Q and Q_hold as zero( to see how data flows into them and out of them.as you can see in the photo bellow, when CLK=1 there is a charging of Q_hold.

But after that when clk=0 i cant see the Q charging from zero to VDD.

I tried to increase the width of the right part to make the charging more  strong.but Q is locked on ZERO value as if Q_hold is not VDD.

You said that you simulated  flipflops an phase detectors , Could you please show me a cadence virtuoso example  of of an actual working  D flip flop, and  a phase detector from it?

Thanks

Dear yefj,

I took some time to study your DFF topology and the resulting time domain waveforms you provided.

> But after that when clk=0 i cant see the Q charging from zero to VDD.
> I tried to increase the width of the right part to make the charging more
> strong.but Q is locked on ZERO value as if Q_hold is not VDD.

Please refer to the attached two figures where I copied your waveforms and added some annotations that I hope will help you understand the operation of your DFF topology. Immediately after the first negative transition of CLK (first file), you are correct that Q does not transition to VDD and this is absolutely correct for the initial conditions you applied. Output Q will only follow the complement of Q_hold when CLK is a logic high. Hence, Q remains at a logic low after the first negative CLK transition. It remains at a logic low since it Q_hold went to a logic high at about 3 ns as Q_hold follows the complement of D when CLK is at a logic high. Hence, for the operation of the DFF appears to be exactly as expected.

Now referring to the second CLK negative transition which I annotated in the second file, immediately after  the second CLK negative transition, Q does now charge to VDD since Q_hold was set to a logic low at about 7 ns when D transitioned to a logic high and CLK was at a logic high.

If you run the transient simulation longer than 10 ns you will "clear out" your initial conditions. I think if you then study the behavior of Q, CLK, D, and Q_hold, I think you will find the DFF is working exactly as expected and correctly. Applying arbitrary initial conditions to a circuit with memory, such as a DFF, will often result is what appears to be "unexpected" behavior. Hence, I usually run simulations such as these for a number of clock transitions and then study behavior after all initial voltages on memory nodes have dissipated and then study circuit behavior.

> You said that you simulated  flipflops an phase detectors , Could you please
> show me a cadence virtuoso example  of of an actual working  D flip flop, and
> a phase detector from it?

I think your circuit is working fine and you don't need another example. Do you agree?

Shawn

Hello Shawn , i agree that the flip flop work correctly.In order to make phase detector I have connected a PMOS MOSFET to make the Q_down/Q_up output zero when RESET=0.

The clock suppused to make the Q_UP/Q_down be VDD again when reset=1, but reset cannot be 1 because because Q_up and q_down is both zero.

So its like a cycle :-) i dont know how to break.

where did i go wrong?

Thanks

Dear yefj,

If you look at your initial diagram of the phase detector you provided, the D inputs are at VDD (a logic high). The reset function sets the Q outputs to a logic low  when reset is asserted (i.e., both q outputs are at a logic high => DN gate output is asserted and resets each DFF to a logic low).

However, in your DFF, your reset function forces the DFF output to a logic high and the D inputs are at a logic high. Hence, your feedback gate choice and/or your implementation of the reset functionality in your DFF are not consistent with your initial phase detector diagram.

Shawn