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multiple gnd's passive components only system problem

robert 21

Hello , i have a system with multiple device represented by R L C components each device has its own ground, i wanted to make POLE ZERO simulation on it.

at first for the simplisity i made  all the devices stacked and one big cirtuit(which was verified in a much simpler simulator called LTSPICE)

After that i tried to convert each device as a symbol as shown bellow.
when In cadence virtuoso i didnt use symbol to simplify the schematics it gave me errors like,

1.no DC path from node "net.. to ground" Gmin installed to provide a path

2.Fatal: the following braches form a loop of rigid barnches(shorts) when added to the circuit

3.why i tried to make subsimbols it gave me an error in bettween the connection of the devices saying they are floating although they are not(and i ran it fine in LTSPICE)

i really want to use the potential of cadence virtuoso to analyze to the fullest extent this passive component network

Where did i go wrong?

Thanks

  • Dear robert21,

    robert 21 said:
    1.no DC path from node "net.. to ground" Gmin installed to provide a path

    Perhaps I am overlooking something in your circuit, but if I zoom in as much as I can to enhance my view of your screenshots, the error reported is justified as your circuits do not have a DC connection to ground. I've annotated two of your screenshots to illustrate that you have not provided a DC path to ground and attached the two files. Therefore, to enhance DC convergence, spectre indicates it is adding a small conductance to provide a DC path to ground. LTSPICE I believe is based on SPICE. It does not warn you, but likely also adds a small conductance to achieve DC convergence. If you study the LTSPICE simulator parameters, you will likely find an analogous parameter to Gmin. HSPICE, for example, includes a gmin whose value is a factor of 10 greater than the default for spectre (1e-11 in lieu of 1e-12 mhos).

    With respect to the fatal error, I do not know the value of your resistors. However, if they are too small and you are simulating with spectre APS, they may be shorted out. One possible way to avoid this is to set the "preserve_inst" option to all. You can do this in ADE using the high performance simulation GUI shown in the attached figure.

    Also, please verify that none of your subcircuits have multiple DC sources driving same node to different DC voltages in all of your subcircuits. This will also cause this fatal error.

    Shawn

  • in reply to FormerMember

    I too struggle to see what's in the schematic, but it doesn't look like the gnd symbol from analogLib, for example.

    Please post the input.scs file (your spectre netlist) as that will make it much clearer how the circuit is configured and what the likely problems are.

    Regards,

    Andrew.

  • in reply to Andrew Beckett

    Hello Andrew, i will try and  look for this file in my directories.

    I have managed to run AC sweep with no problem, the problem starts with when i try to run pole zero simulation

    i get all these error when running pole zero as shown bellow.

    i

  • in reply to ShawnLogan

    Hello Shawn AC simulation goes fine ,problem starts when i tried to run POLE zero as i replied to Andrew

    "You can do this in ADE using the high performance simulation GUI shown in the attached figure."

    how can i enter the high performance simulation GUI?

    Thanks

  • in reply to robert 21

    I wouldn’t worry about the high performance form because it’s more likely your issues are due to a circuit issue rather than an optimisation performed by APS (if you’ve not used that the chances are you’re not using APS anyway so it’s irrelevant).

    I’m also surprised that you’d get rigid branch errors only when using pz and not ac - that’s quite hard to achieve because the checks are done before the analysis. It really would help if you’d given the precise error line from the log file rather than just a vague reference to them. 

    As for the input.scs, you can use Similation->Netlist->Display (ideally from the case that doesn’t work - although also in the case where it does work would be interesting) and the full path to the input.scs can be seen in the banner of the window showing the netlist. Or you can use the File menu in the netlist display window to save it elsewhere (I think). Then please upload these files as attachments to the forum. Otherwise we’ll just go around in circles trying to guess what’s wrong when seeing the actual netlist will make it obvious.

    Thanks,

    Andrew

  • in reply to Andrew Beckett

    Hello Andrew, i made a simpler circuit just to test the basic case and tried AC again and i showed me those errors  again as shown in the attached netlist.txt and report.txt

    Thanks

    Fullscreen error report.txt Download 
    Warning from spectre during circuit read-in.
    WARNING (SFE-2654): VerilogA module `respoly_va' override primitive/(verilogA module) `respoly_va'.
    WARNING (SFE-2654): VerilogA module `respoly_va' override primitive/(verilogA module) `respoly_va'.
Warning from spectre during hierarchy flattening.
    WARNING (SFE-1131): Duplicate scope option `tnom' with scope `TopCircuit'. (using last value specified).

Time for Elaboration: CPU = 26.997 ms, elapsed = 28.7302 ms.
Time accumulated: CPU = 271.958 ms, elapsed = 403.317 ms.
Peak resident memory used = 51.7 Mbytes.

Time for EDB Visiting: CPU = 999 us, elapsed = 718.832 us.
Time accumulated: CPU = 272.957 ms, elapsed = 404.256 ms.
Peak resident memory used = 52.1 Mbytes.


Notice from spectre during topology check.
    No DC path from node `net013' to ground, Gmin installed to provide path.
    No DC path from node `net06' to ground, Gmin installed to provide path.
    No DC path from node `net018' to ground, Gmin installed to provide path.
        V0:p (from net018 to net017)
    No DC path from node `net013' to ground, Gmin installed to provide path.
    No DC path from node `net06' to ground, Gmin installed to provide path.
        Further occurrences of this notice will be suppressed.
Fatal error found by spectre during topology check.
    FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
        V0:p (from net018 to net017)


Aggregate audit (11:42:48 PM, Tue Sep 3, 2019):
Time used: CPU = 274 ms, elapsed = 405 ms, util. = 67.6%.
Time spent in licensing: elapsed = 15.9 ms.
Peak memory used = 52.5 Mbytes.
Simulation started at: 11:42:47 PM, Tue Sep 3, 2019, ended at: 11:42:48 PM, Tue Sep 3, 2019, with elapsed time (wall clock): 405 ms.
spectre completes with 1 error, 3 warnings, and 6 notices.
spectre terminated prematurely due to fatal error.

    Fullscreen netlist.txt Download 
    // Generated for: spectre
// Generated on: Sep  3 23:42:46 2019
// Design library name: projectss
// Design cell name: snr_main
// Design view name: schematic
simulator lang=spectre
global 0
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_25IO_NVT_V021.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_25IO_V111.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_NCAP25_V113.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_varmis_25_rf_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_33IO_GOX52_VT21.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_25IO_RF_V021.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90-resistor-control-V041.scs"
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_BJT_V111.lib.scs" section=tt_bip
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_DIODE_V101.mdl.scs"
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_LL12_RF_V021.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_LLLVT12_RF_VTAB.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_LL12_V102.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_LLHVT12_V101.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_LLLVT12_V102.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_LLNVT12_V011.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90SP_NCAP10_V112.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_NCAP12_LL_V102.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_SP10_V061.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_SPHVT10_V111.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_SPLVT10_V102.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_SPNVT10_V011.lib.scs" section=tt
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_mimcaps_20f_kf_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_momcaps_V041.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_vardiop_rf_v011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_varmis_12_llrf_V021.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/momcaps_array_vp3_rfvcl_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/momcaps_array_vp4_rfvcl_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/rnhr_rf_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/rnnpo_rf_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/rnppo_rf_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_varmis_10_sprf_V011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/bond_pad_v011.lib.scs" section=typ
include "/eda_disk/pdks/UMC/UMC90nm/umc90nm/../Models/Spectre/L90_SP10_RF_V021.lib.scs" section=tt

// Library name: projectss
// Cell name: snr_main
// View name: schematic
R0 (net1 net5) resistor r=50
C19 (net016 net018) capacitor c=1p
C18 (net016 0) capacitor c=1p
C17 (net018 0) capacitor c=1p
C16 (net018 net017) capacitor c=1p
C15 (net013 net025) capacitor c=1p
C14 (net013 0) capacitor c=1p
C13 (net014 0) capacitor c=1p
C12 (net014 net013) capacitor c=1p
C11 (net06 net05) capacitor c=1p
C10 (net06 0) capacitor c=1p
C9 (net05 0) capacitor c=1p
C8 (net05 net022) capacitor c=1p
C7 (net07 net023) capacitor c=1p
C6 (net07 0) capacitor c=1p
C5 (net08 0) capacitor c=1p
C4 (net08 net07) capacitor c=1p
C3 (0 net1) capacitor c=1p
C2 (net1 net6) capacitor c=390p
C0 (net1 net5) capacitor c=390p
L15 (net018 net017) inductor l=1n
L14 (net017 net026) inductor l=1n
L13 (net026 net014) inductor l=1n
L12 (net025 net6) inductor l=1n
L11 (net013 net025) inductor l=1n
L10 (net5 net016) inductor l=1n
L9 (net05 net022) inductor l=1n
L8 (net022 net6) inductor l=1n
L7 (net027 net06) inductor l=1n
L6 (net023 net027) inductor l=1n
L5 (net07 net023) inductor l=1n
L4 (net5 net08) inductor l=1n
L2 (net1 net6) inductor l=2u
L0 (net1 net5) inductor l=10n
V0 (net018 net017) vsource mag=1 type=dc
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
    tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
    digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
    checklimitdest=psf 
ac ac start=25k stop=40M annotate=status 
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub

  • in reply to robert 21

    Dear robert21,

    Inspection of your netlist indicates that you have an ideal inductor (with zero series resistance) in parallel with your ideal 1 V DC source voltage. Hence, you have tried to short out your ideal voltage source.

    L15 (net018 net017) inductor l=1n
    V0 (net018 net017) vsource mag=1 type=dc

    This is exactly the error spectre is producing:

    Fatal error found by spectre during topology check.
        FATAL: The following branches form a loop of rigid branches (shorts) when added to the circuit:
            V0:p (from net018 to net017)

    Shawn

  • in reply to ShawnLogan

    In addition to what Shawn correctly points out (thanks Shawn), we can't debug the other issues in your higher level circuit (for example, the "ground" symbols don't look like ground symbols to me, so I don't know whether each block is really grounded) since you simplified it too much. In fact it's not even the same as the sub-block you posted because this only has one resistor in it (the schematic above has 3) and has many more inductors and capacitors. It appears to be a totally different circuit.

    After correcting the loop of rigid branches, I get:

    No DC path from node `net013' to ground, Gmin installed to provide path.
    No DC path from node `net06' to ground, Gmin installed to provide path.
    No DC path from node `net018' to ground, Gmin installed to provide path.

    This is because during the DC the capacitors are removed (open-circuit) and the inductors are shorted (closed-circuit), and so these nodes end up floating. So it's the reasons that Shawn gave earlier.

    Andrew

  • in reply to Andrew Beckett

    I added parralel resistance to the inductor and it worked,

    Thanks

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