single path idial current not floowing threw transistor

The only thing I can imagine is that the device models have other components in around the transistor which might provide an alternative current path. Sometimes you see currents flowing through the gmin resistors but that's not going to be it here (otherwise you'd have huge voltages).

So without seeing the actual simulation data, it's hard to comment. If you post the input.scs and also provide the name and reference number of the device models (PDK) you're using, then I should be able to figure it out - it's very unlikely that it's a simulator problem because spectre cannot lose the current... it honours Kirchoff's Current Law (at least to the tolerances set in the simulator).

Andrew.

Hello Andrew,If i remmember correctly input.scs is the simulation display file on the terminal.

i have attached the output log. i am using global foundry 28nm ,egnfet transistor.

Thanks

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~
Entering remote command mode using MPSC service (spectre, ipi, v0.0, spectre0_30173_7, ).

Warning from spectre.
	WARNING (SPECTRE-16707): Only tran supports psfxl format, result of other analyses will be in psfbin format.


******************
DC Analysis `dcOp'
******************

Notice from spectre during DC analysis `dcOp'.
	No checklimit analysis defined for asserts. A default checklimit analysis 'SpectreChecklimitAnal' has been created with all asserts enabled.

The following asserts will be enabled for all subsequent analyses until the next checklimit analysis statement is found:
temperature_min_check : ON
temperature_max_check : ON
N21.egnfet_gate_source_terminal_check : ON
N21.egnfet_drain_source_terminal_check : ON
N21.egnfet_body_source_terminal_check : ON
N21.egnfet_drain_body_terminal_check : ON
N21.egnfet_gate_drain_terminal_check : ON
N21.egnfet_gate_body_terminal_check : ON
N20.egnfet_gate_source_terminal_check : ON
N20.egnfet_drain_source_terminal_check : ON
N20.egnfet_body_source_terminal_check : ON
N20.egnfet_drain_body_terminal_check : ON
N20.egnfet_gate_drain_terminal_check : ON
N20.egnfet_gate_body_terminal_check : ON
N0.egnfet_gate_source_terminal_check : ON
N0.egnfet_drain_source_terminal_check : ON
N0.egnfet_body_source_terminal_check : ON
N0.egnfet_drain_body_terminal_check : ON
N0.egnfet_gate_drain_terminal_check : ON
N0.egnfet_gate_body_terminal_check : ON
N19.egnfet_gate_source_terminal_check : ON
N19.egnfet_drain_source_terminal_check : ON
N19.egnfet_body_source_terminal_check : ON
N19.egnfet_drain_body_terminal_check : ON
N19.egnfet_gate_drain_terminal_check : ON
N19.egnfet_gate_body_terminal_check : ON

Opening the PSF file ../psf/dcOp.dc ...
Important parameter values:
	reltol = 1e-03
	abstol(V) = 1 uV
	abstol(I) = 1 pA
	temp = 27 C
	tnom = 27 C
	tempeffects = all
	gmindc = 1 pS
Trying `homotopy = gmin'.

Maximum value achieved for any signal of each quantity:
V: V(net01) = 4.149 V
I: I(V6:p) = 50 uA
Convergence achieved in 216 iterations.
DC simulation time: CPU = 634.902 ms, elapsed = 1.70052 s.
Total time required for dc analysis `dcOp': CPU = 32.994 ms, elapsed = 65.5391 ms.
Time accumulated: CPU = 634.902 ms, elapsed = 1.70167 s.
Peak resident memory used = 86.3 Mbytes.

dcOpInfo: writing operating point information to rawfile.

Opening the PSF file ../psf/dcOpInfo.info ...
modelParameter: writing model parameter values to rawfile.

Opening the PSF file ../psf/modelParameter.info ...
element: writing instance parameter values to rawfile.

Opening the PSF file ../psf/element.info ...
outputParameter: writing output parameter values to rawfile.

Opening the PSF file ../psf/outputParameter.info ...
designParamVals: writing netlist parameters to rawfile.

Opening the PSFASCII file ../psf/designParamVals.info ...
primitives: writing primitives to rawfile.

Opening the PSFASCII file ../psf/primitives.info.primitives ...
subckts: writing subcircuits to rawfile.

Opening the PSFASCII file ../psf/subckts.info.subckts ...

Dear robert21,

robert 21 said:

As you cant see bellow , all the transistors expect one are saturated,so the transistor is not in cuttoff.The whole 50uA supposed too run threw both series connected transistors .

I have tried connecting the bulk to ground to avoid completly the option of diode leakage(as shown bello)

Why only partial amount of the idial current source flowing threw the mosfet?

I am not sure of your MOS technology limits robert21, however, I suspect that the "missing" current is flowing through the gates and bulk diodes of your devices M19 and M20. Please note the gate voltage of these devices is over 4V (as a result of your ideal current source's infinite output impedance)! My guess is that this is forcing current through the device gates. As a test, you might reduce the 50 uA bias current in a series of DC operating point simulations to say, 1 uA, and plot the DC current through M19 or M20 as a function of your currrent source current. If my hypothesis is valid, at some lower value of current source value, the gate voltages of M19 and M20 will drop to less than 1.8 V and, ultimately, the drain source current of M19 will equal that of your DC current source value.

Shawn

Hello Shawn, i have switched to UMC90nm to test this issue ,and i got the same abnomal  "leakage".

You were corrent that lowering the DC idial current source to 10uA makes everything correct.

At 50uA we got the 5V at the output of the idial current source but at 10uA idial source value we have all the 10uA flowing threw the mosfet diode connection(as shown bellow)

i have problem believing that on both technologies we have oxide layer break and gate leakage at 50uA.

Why connecting 1.8 VDD straight to idial current source connected straight to mosfet diode can cause such anomaly at 50ua?

Maybe there is a clash between the idial VDD with the idial Idc ?

UPDATE:

Everything worked when i increased W from 1u to 8u on both transistors of the branch.

Still i cant see why low W caused this problem, in the original post all transistors were in saturation so current should have passed threw them with no problem.

Why transistor Width caused such a thing?

Thanks.

50uA idial current source

10uA:

robert 21 said:

Why transistor Width caused such a thing?

Dear robert21,

Did you study the I-V characteristic of the 1 um width device and compare it to the 8 um device? I believe the answer lies in the I-V characteristics. The 1 um device may not support 50 ua without excessive voltages at its terminals.

Shawn