Using Ideal Frequency Divider Block in Cadence

The comments at the top of the model in the VerilogA view suggest that it's hard to get this to work with big divide ratios (I would agree - it's using a titrating capacitor approach). I think you'd need the tt parameter to be much smaller.

I can get it to work with these settings:

n=1000 nhi=500 dir=1 tt=10p vdd=1.2 vss=0 thresh=0

and then running with transient or pss with errpreset=conservative (it was a struggle with the default of errpreset=moderate).

I also used nhi=500 to give an even mark-space ratio.

The comments also suggest it's not particularly efficient for transient, but the whole point is not for use with transient but as model that will work in RF analyses.

Andrew

Thanks Andrew that helped me get started with the simulations. I have some follow up queries.

The reason why I am troubleshooting my PLL is because my loop phase noise is very bad, it's around -40dBc/Hz. My VCO phase noise is good, it is around -100dBc/Hz. For my loop filter, in the charge pump block, I am using zeta and natural frequency formulas to calculate the filter parameters (R1, C1, C2) so assuming that the filter part is OK my initial guess was that the phase noise misbehavior is coming from the frequency divider (it has a massive divide ratio of 1000). I replaced the divider with an ideal divider block, and surprisingly enough the loop phase noise is much worse now. I have two guesses now, either the phase noise misbehavior is coming from some other block (attaching the block diagram for reference) or my simulation set up is wrong (I am attaching my sim set up as well, hb and hbnoise). Any help on how to resolve or troubleshoot this issue further is appreciated. Also attaching my phase noise profile, please notice it has a huge bandwidth, which is basically my issue I believe. Thank you! 

Dear astroshey,

Wow! I am not sure where to begin with my few comments to your post. Let me make a couple of comments and show a plot or two.

astroshey said:

The reason why I am troubleshooting my PLL is because my loop phase noise is very bad, it's around -40dBc/Hz. My VCO phase noise is good, it is around -100dBc/Hz. For my loop filter, in the charge pump block, I am using zeta and natural frequency formulas to calculate the filter parameters (R1, C1, C2) so assuming that the filter part is OK my initial guess was that the phase noise misbehavior is coming from the frequency divider (it has a massive divide ratio of 1000). I replaced the divider with an ideal divider block, and surprisingly enough the loop phase noise is much worse now. I have two guesses now, either the phase noise misbehavior is coming from some other block (attaching the block diagram for reference) or my simulation set up is wrong (I am attaching my sim set up as well, hb and hbnoise). Any help on how to resolve or troubleshoot this issue further is appreciated. Also attaching my phase noise profile, please notice it has a huge bandwidth,

I don't know your loop parameters, so made an estimate to create a reasonable loop bandwidth of about 5 MHz for your 100 MHz input reference clock. I then simulated the jitter transfer (gain and phase) for both a small and large signal case. The large signal simulation is essentially a transient simulation. The gain and phase for the two are shown in Figure 1 and Figure 2. The two are consistent with the exception of the phase near your 100 MHz reference clock since the large signal simulation shows evidence of the reference clock due to incomplete filtering. If your loop bandwidth exceeds about 10 MHz, the large signal behavior will not correlate well with your small signal behavior.

www.dropbox.com/s/b5armzbfniubef7/ss_ls_pll_pfd_100g_vco_100meg_ref_031323v1p0.pdf?dl=0

I then ran a series of large-signal simulations where I apply random band limited input noise to the PFD. THe noise bandwidth varies from 1 MHz to 10 GHz. Figure 3 shows the output phase in response to each input noise bandwidth. Note that the output phase noise at offset frequencies less than the 5 MHz loop bandwidth grows significantly as the noise bandwidth exceeds the reference clock rate. This is expected since you will get aliasing of the higher frequency noise components to frequencies less than 100 MHz. I suspect this is why your phase noise is increasing. 

If you can share a few more details on your loop parameters, I can simulate them and provide some added insight, perhaps.

Shawn

Hi astroshey,

In general, we don't recommend using SpectreRF for PLLs.   (For the full text, see Article  20468264: How should I simulate my PLL circuit in SpectreRF? https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O0V00000679z2UAA   (Note:  You must have a login for the Cadence Support site.  You can request one on the Support main page.  If you are a University student, you'll need to talk to the Professor who manages your Cadence account.)

Why?

• PLL circuits are notoriously difficult to get convergence with in Spectre RF. All signals in the circuit must be periodic, and the circuit must respond periodically; otherwise, you will not get convergence. One example is described in Article 20134975  PSS not converging on PLL circuit.
• Simulating PLL circuits are typically best accomplished with transient and transient noise analysis.

Cadence recommends using the method presented in the PLL Verification (Using ADE Explorer and XCELIUM) Rapid Adoption Kit​

You may also want to look at the Virtuoso Transient Noise Appnotes:

• Spectre Transient Noise Simulation from ADE - Advanced 
• Spectre Transient Noise Simulation from ADE – An Introduction
• You could also use an event-like behavioral simulation of an overall PLL, as in the methodology described in Ken Kundert's paper Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers,​ Ken Kundert Designer’s Guide Consulting, Inc.  Jitter measurements can be directly inserted into the type of macromodels used in that paper. Usually, the extracted metric in this type of methodology is the sampled jitter (pmjitter) and it is used directly. The Designer’s Guide is an excellent website (http://www.designers-guide.org/Analysis/) which has a section on phase noise and jitter, which you may find helpful.

If you want to simulate part of the PLL (say the oscillator with a divider circuit) I recommend:

Article (20491924)
Title: How to set up pss/pnoise sampled(jitter) when simulating a driven circuit or a VCO, both containing dividers
URL: https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1O3w000009xzDeEAI&pageName=ArticleContent

best regards,

Tawna

Hi Shawn, 

Thank you very much for the insights and plots! I see that for the BW you went with one-twentieth of the reference frequency which equals 5MHz. I went with one-tenth, so my loop BW is 10MHz. From then on I got C1=134p, C2=0.2*C1=26.8p, and Rp=500 Ohm using the zeta and wn formulas. My Kvco=2*pi*10G, my Ip=15mA (I am not certain if I calculated this correctly, it seems too large to me) and the divide ratio is 1000. I would appreciate any further insights you have based on the information I provided, thank you again for your help!

Hi Tawna, 

I am looking into getting access to Cadence Support so that I can read through the material you shared. However, my PLL loop does converge in a reasonable amount of time (~2-3hrs). I am using hb and hbnoise analysis which have been recommended to me by my professors. Would you recommend any other analysis for PLL loop simulation, specially for phase noise? BTW I was successfully able to simulate VCO and divider blocks together, I am now focusing on loop phase noise. Thank you for your help! 

Dear astroshey,

astroshey said:

I see that for the BW you went with one-twentieth of the reference frequency which equals 5MHz. I went with one-tenth, so my loop BW is 10MHz. From then on I got C1=134p, C2=0.2*C1=26.8p, and Rp=500 Ohm using the zeta and wn formulas. My Kvco=2*pi*10G, my Ip=15mA (I am not certain if I calculated this correctly, it seems too large to me) and the divide ratio is 1000.

I examined your loop parameters, and given your other loop parameters, a charge pump current of 15 mA is a factor of 10 too large to produce a small-signal bandwidth of about 10 MHz.  Hence, I chose a charge pump current of 1.5 mA to perform the small and large signal simulations.

I have updated the note at URL:

www.dropbox.com/s/hg2o6c1wk8lirfj/ss_ls_pll_pfd_100g_vco_100meg_ref_031423v1p1.pdf?dl=0

to include the small and large signal transfer functions. The peaking in the transfer function does result in some ringing in the phase response. I've illustrated it for one of the simulations showing the input and output phase  in Figure 1.

astroshey said:

and the divide ratio is 1000. I would appreciate any further insights you have based on the information I provided,

Andrew Beckett said:

The comments at the top of the model in the VerilogA view suggest that it's hard to get this to work with big divide ratios (I would agree - it's using a titrating capacitor approach). I think you'd need the tt parameter to be much smaller.

I forgot to mention in my initial response that a possible way to avoid the large divider ratio is to cascade two of the verilog-A divider instances each of which has a divide ratio of 10. However, one parameter that your divider may not be accurately modeling is the delay of the divider. The divider delay will impact loop stability (i.e. jitter peaking and transient response). If you know the approximate delay of your transistor level divider, it may be worth including this delay in your transient simulation.

astroshey said:

Would you recommend any other analysis for PLL loop simulation, specially for phase noise?

I will not pretend to comment on your question for Tawna nor for Andrew!

However, we recently did have a Forum post where this topic was discussed, and there are several opinions provided. The Forum post is at URL:

https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/55593/observing-pll-phase-noise-with-hbnoise/1388668#1388668

Shawn

Figure 1

Hi Shawn, 

Thank you for the additional analysis and suggestions! You mean I can cascade three divide by 10 frequency dividers to get a divide ratio of 1000, instead using 1 divide by 1000 verilogA block? Also, as per your suggestion, I changed the value of Ip, and now I am getting a better phase noise but still it's not quite reasonable yet. Please see attached. I am still working on improving it, if I could get it to -70dBc/Hz at 1MHz offset that would be good for now. In my transistor-based charge pump, where should I pay close attention to besides the loop filter in order to get a narrow bandwidth? Thank you!

Dear atroshey,

astroshey said:

ou mean I can cascade three divide by 10 frequency dividers to get a divide ratio of 1000, instead using 1 divide by 1000 verilogA block?

I was not clear and apologize! Yes, I was proposing that you replace the single verilog-A block whose divider setting is 1000 to, for example, 2 cascaded verilog-A blocks with respective divider settings of 10 and 100. Of course, you could also cascade three verilog-A divider blocks with each of the three set having divider settings of 10. The basic thought is to use much smaller divider settings in the block to avoid the limitation the code presents for a large divide ratio.

astroshey said:

I changed the value of Ip, and now I am getting a better phase noise but still it's not quite reasonable yet. Please see attached.

With the charge pump current of 15 mA, or with your updated value of 1.5 mA, did you look at the transient response of your loop? If you saved the initial transient of your pss simulation, you might examine its loop response. I did not find the 15 mA charge pump current as unstable from a small-signal perspective, but the loop bandwidth was about 44 MHz and the peaking was over 8 dB. I was concerned about its large signal transient response.

I don't know what kind of a VCO you are using. You did note its phase noise was -100 dBc/ Hz bu did not include the offset frequency for that measurement. I don't see any evidence of its phase noise in your plot. I also do not know the noise of your 100 MHz iinput reference clock - which also plays a role in the output phase noise.

In summary, your phase noise plot does not look right for a few reasons. If you examine the phase noise of the large simulation I ran where the input noise has a 100 MHz bandwidth and the phase-locked loop bandwidth is 10 MHz on page 10 (Figure 10) at URL:

www.dropbox.com/s/hg2o6c1wk8lirfj/ss_ls_pll_pfd_100g_vco_100meg_ref_031423v1p1.pdf?dl=0

you will note the output phase noise starts to drop off rapidly for offset frequencies greater than 10 MHz.

To better illustrate a few major concerns, I updated the note to include an annotated version of your Forum phase noise plot above with my concerns on page 15. On page 16, I included the measured output phase noise of a phase-lock loop and indicate the salient features that are missing from your simulated phase noise plot.

I think it might be worth stepping back to make sure your phase-locked loop is showing the transient response you expect, has a reasonable static phase offset in steady-state, and has a settling time commensurate with the time chosen to start the pss analysis. Perhaps a few conventional transient simulations might be chosen to validate the expected performance prior to performing additional pss/pnoise analyses? These are all my opinions only!

Shawn

Dear astroshey,

My response was flagged as spam and will hopefully be released soon in order that you might read over my comments.

Shawn