Using Ideal Frequency Divider Block in Cadence

The comments at the top of the model in the VerilogA view suggest that it's hard to get this to work with big divide ratios (I would agree - it's using a titrating capacitor approach). I think you'd need the tt parameter to be much smaller.

I can get it to work with these settings:

n=1000 nhi=500 dir=1 tt=10p vdd=1.2 vss=0 thresh=0

and then running with transient or pss with errpreset=conservative (it was a struggle with the default of errpreset=moderate).

I also used nhi=500 to give an even mark-space ratio.

The comments also suggest it's not particularly efficient for transient, but the whole point is not for use with transient but as model that will work in RF analyses.

Andrew

Thanks Andrew that helped me get started with the simulations. I have some follow up queries.

The reason why I am troubleshooting my PLL is because my loop phase noise is very bad, it's around -40dBc/Hz. My VCO phase noise is good, it is around -100dBc/Hz. For my loop filter, in the charge pump block, I am using zeta and natural frequency formulas to calculate the filter parameters (R1, C1, C2) so assuming that the filter part is OK my initial guess was that the phase noise misbehavior is coming from the frequency divider (it has a massive divide ratio of 1000). I replaced the divider with an ideal divider block, and surprisingly enough the loop phase noise is much worse now. I have two guesses now, either the phase noise misbehavior is coming from some other block (attaching the block diagram for reference) or my simulation set up is wrong (I am attaching my sim set up as well, hb and hbnoise). Any help on how to resolve or troubleshoot this issue further is appreciated. Also attaching my phase noise profile, please notice it has a huge bandwidth, which is basically my issue I believe. Thank you! 

Dear astroshey,

Wow! I am not sure where to begin with my few comments to your post. Let me make a couple of comments and show a plot or two.

astroshey said:

The reason why I am troubleshooting my PLL is because my loop phase noise is very bad, it's around -40dBc/Hz. My VCO phase noise is good, it is around -100dBc/Hz. For my loop filter, in the charge pump block, I am using zeta and natural frequency formulas to calculate the filter parameters (R1, C1, C2) so assuming that the filter part is OK my initial guess was that the phase noise misbehavior is coming from the frequency divider (it has a massive divide ratio of 1000). I replaced the divider with an ideal divider block, and surprisingly enough the loop phase noise is much worse now. I have two guesses now, either the phase noise misbehavior is coming from some other block (attaching the block diagram for reference) or my simulation set up is wrong (I am attaching my sim set up as well, hb and hbnoise). Any help on how to resolve or troubleshoot this issue further is appreciated. Also attaching my phase noise profile, please notice it has a huge bandwidth,

I don't know your loop parameters, so made an estimate to create a reasonable loop bandwidth of about 5 MHz for your 100 MHz input reference clock. I then simulated the jitter transfer (gain and phase) for both a small and large signal case. The large signal simulation is essentially a transient simulation. The gain and phase for the two are shown in Figure 1 and Figure 2. The two are consistent with the exception of the phase near your 100 MHz reference clock since the large signal simulation shows evidence of the reference clock due to incomplete filtering. If your loop bandwidth exceeds about 10 MHz, the large signal behavior will not correlate well with your small signal behavior.

www.dropbox.com/s/b5armzbfniubef7/ss_ls_pll_pfd_100g_vco_100meg_ref_031323v1p0.pdf?dl=0

I then ran a series of large-signal simulations where I apply random band limited input noise to the PFD. THe noise bandwidth varies from 1 MHz to 10 GHz. Figure 3 shows the output phase in response to each input noise bandwidth. Note that the output phase noise at offset frequencies less than the 5 MHz loop bandwidth grows significantly as the noise bandwidth exceeds the reference clock rate. This is expected since you will get aliasing of the higher frequency noise components to frequencies less than 100 MHz. I suspect this is why your phase noise is increasing. 

If you can share a few more details on your loop parameters, I can simulate them and provide some added insight, perhaps.

Shawn

Hi Shawn, 

Thank you very much for the insights and plots! I see that for the BW you went with one-twentieth of the reference frequency which equals 5MHz. I went with one-tenth, so my loop BW is 10MHz. From then on I got C1=134p, C2=0.2*C1=26.8p, and Rp=500 Ohm using the zeta and wn formulas. My Kvco=2*pi*10G, my Ip=15mA (I am not certain if I calculated this correctly, it seems too large to me) and the divide ratio is 1000. I would appreciate any further insights you have based on the information I provided, thank you again for your help!

Hi Shawn, 

Thank you very much for the insights and plots! I see that for the BW you went with one-twentieth of the reference frequency which equals 5MHz. I went with one-tenth, so my loop BW is 10MHz. From then on I got C1=134p, C2=0.2*C1=26.8p, and Rp=500 Ohm using the zeta and wn formulas. My Kvco=2*pi*10G, my Ip=15mA (I am not certain if I calculated this correctly, it seems too large to me) and the divide ratio is 1000. I would appreciate any further insights you have based on the information I provided, thank you again for your help!