NC Verilog issue

Offline PRVN 11 months ago

Hi,

I am using NC Verilog for verification to my IP design, but I unable to run system_Verilog fils in that,

So, how can I run system Verilog fils in NC Verilog tool? what is the command for that?

Thanks & Regards,

praveen

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

Verification IP Forums

NC Verilog issue

Community Guidelines