I am using cadence denali pcie vip to verify my Endpoint device.
EP DUT had MSI-X size for 32 entries during initial write to table ram from RC vip it initializes only 11 out of 32.
I have a debug statement from denali.his file :
uvm_test_top.pcieSve0.ARcPEpEnv0.activeRc(p_0.cfg_0_0) 119044412 ps Debug: MSIX (req:32 allocated:11)
Please tell me why is this happening, What must be done to initialize total entries.
Thanks for the reply,