Google FeedBurner is phasing out its RSS-to-email subscription service. While we are currently working on the implementation of a new system, you may experience an interruption in your email subscription service. Please stay tuned for further communications.

Verification IP Forums

User-defined Assertion Coverage in Incisive Enterprise Verifier for formal verification

Archana P
9 months ago

I have written a set of user-defined assertions to verify a design formally in Incisive Enterprise Verifier. Is it possible to obtain coverage percentage (block coverage etc) for those assertions? I could find coverage percentage for automatic formal analysis done by the tool on the same design. Everything about coverage for automatic formal analysis is in the manual. My doubt is how to find similar coverage data for user-defined assertions? 

More Content

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.