Stats

  • Replies 3
  • Subscribers 66
  • Views 15026
  • Members are here 0
More Content

Importing vias in Allegro APD

Siraj Akhtar
I want to know how to import via’s into Allegro APD.

 I have a file that contains the coordinates of my package vias. I want to import them into APD so that I don’t have to manually replace each via. I have a VIA_175 padstack already created that I want to use for these vias. How can I import this into APD?

Alternatively, I have tried importing a gds that contains the vias. I can bring this into APD as a conductor or as a shape, but I can’t figure out how to replace these so that they are now VIA’s using the VIA_175 padstack.

Any thoughts?

 
Parents

  •  

    Bill,

     

    Thank you for the response.

     

    I use the following BGA in file:

    _____________

    file: /Allegro/BGA_mychip.txt

    Date: Wed May  5 16:17:01 2010

    Units: microns, 2 decimal places

    Name: BGA_9MMX9MM

    RefDes: BGA

    Origin: (0.00 0.00)

    Rotation: 0.000

    Pad Layer: BOT_COND

    Extents: ((-4500.00 -4500.00) (4500.00 4500.00))

     

    Pin Number       Padstack          X Coord Y Coord            Rotation            Pin Use Net Name

    A2        BGA_PAD_1     -4000    -3500    0          BI         VSS_OSC        

    A3        BGA_PAD_1     -4000    -3000    0          BI         VDD_OSC

    ...

    _______________

     

    So now, if I have the via center points, can I do the following:

     

    file: /Allegro/VIA_mychip.txt

    Date: Wed May  5 16:17:01 2010

    Units: microns, 2 decimal places

    Name: VIA_9MMX9MM

    RefDes: BGA

    Origin: (0.00 0.00)

    Rotation: 0.000

    Pad Layer: ???

    Extents: ((-4500.00 -4500.00) (4500.00 4500.00))

     

    Pin Number       Padstack          X Coord             Y Coord                        Rotation            Pin Use Net Name

    V1                    VIA_175            -1940.41            -2010.79            0          BI         VSS_OSC        

    V2                    VIA_175            -3048.22            -3183.66            0          BI         VDD_OSC

    ...

    _______________

     

     

    What do I specify for Pad Layer in the header? TOP_COND, BOT_COND?

     

    Also when this VIA comes in, will it have the connectivity because it already has the Net Name assigned to it?

     

    Regards.

    --Siraj.

Reply

  •  

    Bill,

     

    Thank you for the response.

     

    I use the following BGA in file:

    _____________

    file: /Allegro/BGA_mychip.txt

    Date: Wed May  5 16:17:01 2010

    Units: microns, 2 decimal places

    Name: BGA_9MMX9MM

    RefDes: BGA

    Origin: (0.00 0.00)

    Rotation: 0.000

    Pad Layer: BOT_COND

    Extents: ((-4500.00 -4500.00) (4500.00 4500.00))

     

    Pin Number       Padstack          X Coord Y Coord            Rotation            Pin Use Net Name

    A2        BGA_PAD_1     -4000    -3500    0          BI         VSS_OSC        

    A3        BGA_PAD_1     -4000    -3000    0          BI         VDD_OSC

    ...

    _______________

     

    So now, if I have the via center points, can I do the following:

     

    file: /Allegro/VIA_mychip.txt

    Date: Wed May  5 16:17:01 2010

    Units: microns, 2 decimal places

    Name: VIA_9MMX9MM

    RefDes: BGA

    Origin: (0.00 0.00)

    Rotation: 0.000

    Pad Layer: ???

    Extents: ((-4500.00 -4500.00) (4500.00 4500.00))

     

    Pin Number       Padstack          X Coord             Y Coord                        Rotation            Pin Use Net Name

    V1                    VIA_175            -1940.41            -2010.79            0          BI         VSS_OSC        

    V2                    VIA_175            -3048.22            -3183.66            0          BI         VDD_OSC

    ...

    _______________

     

     

    What do I specify for Pad Layer in the header? TOP_COND, BOT_COND?

     

    Also when this VIA comes in, will it have the connectivity because it already has the Net Name assigned to it?

     

    Regards.

    --Siraj.

Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.