Stats

Replies 3
Subscribers 65
Views 2200
Members are here 0

Can't create plating bar in SIP

VLSI88 over 11 years ago

I was working with 16.5 SiP version and I couldnot create the plating bar. It kept giving me this message:

Symbol extents are greater than the drawing extents ... increase the drawing extents.

I looked at the dwg extent it was set way more than it should be still did not work.

Please help.

Thanks so much

BillAcito over 11 years ago

What are your design units, and what distance away from the package edge are you entering in for the pbar?
Bill
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel
VLSI88 over 11 years ago

I am using um for unit and the plating bar is only 200um away from the pkg edge.
dwg extent is set at 500000.

Thanks for your help
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel
BillAcito over 11 years ago

If the BGA's component class is incorrect, or if it is missing some of the boundary subclasses (place bound, assembly, etc), you will get this error. You may want to work with your customer support person to figure out the specific issue.
Bill
Cancel
Vote Up 0 Vote Down

Sign in to reply

Cancel

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.