prefprop.txt properties aren't working

more info:

The current schematic will not display the properties, but if I create a new one it will........

it appears to be an issue with Capture Constraint Manager being enabled in the design. Is it possible to disable it? 

I can say for now I won't be missing Capture when we jump ship. It used to be a great tool....

I just ran into this issue as well.  No way to edit/view the properties like I've always been able to do.  I am shocked as well at the decline of this tool and am shopping a replacement after 25yrs of declining innovation and horrendous tool changes forced on us....

So once you enable the CM flow you use CM launched from Capture to add Constraints (the same way you do in PCB Editor). Not sure what the issue with that is..........

Take a look at this Can I disable constraints flow from Allegro Design Entry CIS (OrCAD Capture CIS) to Allegro PCB Editor Netlist? (cadence.com) which may help.

I've seen that. Thanks. Short answer is once you've enable CM in Capture you can't go back, unless you want to use an older version of the schematic.

It's a pretty big issue if you have a CM enabled OrCAD flow and you transfer the design to a license that does not include that.  You can't see/edit any of the properties on the nets that were once available before the CM flow got enabled.  That makes it impossible to manage the design on a lower license.

It's a pretty big issue if you have a CM enabled OrCAD flow and you transfer the design to a license that does not include that.  You can't see/edit any of the properties on the nets that were once available before the CM flow got enabled.  That makes it impossible to manage the design on a lower license.

Hi Red.

That CM Flow got introduced in 17.2. Honestly I have never used it. I know for a fact that Major IC Mfr's that make PC Motherboards also do not use it. More curiosity than anything but what on earth is the advantage on having it in Capture.

It kind of seems wierd to me that engineers or drafters would be setting critical net parameters on the schematic. Seems like it just adds to or can hamper the board creation in particular because if an engineer is unaware of the board topology aka stackup etc the bit twiddling at the schematic level is going to cause problems.

I am probably missing something of value here, any clues as to why use it ?. I am kind of drawing a blank on this.

Thanks.

Same here: never use (and not planing to): parameters from schematic are only NET_PHYSICAL_TYPE NET_SPACING_TYPE NET_ELECTRICAL_TYPE and sometimes DIFF_PAIR in order to group things.