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ORCAP-1589: Net has two or more aliases that might lead to a short.

Fredda

Can't find anything useful about the ORCAP-1589 DRC warning so I'm asking here. I get this:

WARNING(ORCAP-1589): Net has two or more aliases that might lead to a short. Ensure nets are not shorted together or nets do not have two or more aliases. This message is displayed because 'Report all net names' is set in Design Rules Check dialog. U1,VCCO_PSDDR_504 VCCO_PSDDR_504 +1.1V

which is a total useless warning that I want to get rid of. I don't understand why in the first place Capture insists to use the name of the power pin of a part as an alias for the net. How can I change this or get rid of the Warning? By the way, disabling the "Report all net names" in the Design Rule Check Report Setup doesn't help, which the Warning message makes it look like.

/F

Parents
  • +1

    This is a legacy from when Orcad was invented 40 years ago. The "standard" was a 5V supply called Vcc or Vdd, and a positive and negative higher voltage supply for analog stuff. Instead of wiring all the power pins on the schematic together, Orcad decided to connect them "behind the scenes" based on their names. This was an excellent strategy for at least 10 years. For the last 20 years at least this is a pain. It forces us to declare all power pins as passive to avoid this pseudo-error. I wish Cadence would add an option to disable this feature. I am not hopeful, the software people don't really know how the hardware people work, and it seems that Cadence has a very limited budget for improvements in Capture. They still need to figure out that there is credible competition, and when the schematic capture tool changes Allegro is also no longer used.

  • 0 in reply to yksv

    I completely agree, I am also looking for how to disable this warning. I am tired to correct third party symbols and make them all passive. 

Reply Children
  • 0 in reply to SergeS

    I don't trust third party symbols or footprints.  Example of footprint issues: UltraLibraian (Not UL which is a trade mark of Underwriters Laboratory), EPads that require thermal via's are not in the padstack.  We have asked them to add them, but they told use that can't do it. Disappointed Also most of the BTC (Bottom Terminated Component) footprints don't comply with the IPC 7093A BTC Standard.

    As a reviewer I have found way to many symbols with only passive pins - avoids DRC's, but why?

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