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Capture vs PCB Editor: Pin number mismatch Error message

Ulf K

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(Capture CIS / OrCAD Layout Prof.)  v. 23.1)

I have a design where the (Capture) Schematic contains two SOT-89 symbols.

Their pins are designated "1", "2", "3"; and "TAB". The corresponding footprint has pads named exactly the same: "1", "2", "3", and "TAB".

Creating the layout, editing it, adding or changing components in the schematic is successfully synchronized every time.

The layout editor opens, it "Pulls" the schematic and the changes are applied.

But: I constantly have two warnings in Capture that the number of pins does not match:

Warning Physical (WARNING OrCAP-2435) Number of pins in footprint "SOT-89" and instance "U3" does not match (Same message for the other, U4...) 

Did some programmer never thought of the possibility that pins could be numbered with other characters than numbers?

Or does Capture and PCB-Editor have different opinions about "numbers" ?

Parents
  • +1

    It was discovered that two footprints with same name but different number of pins existed.

    They were in two different sub-folders.  Both sub-folders were listed in the .PSM search path configuration.

    When one of the SOT89 foot prints was renamed, the error message disappeared....

    (Lesson learned)

  • 0 in reply to Ulf K

    What was the Part Numbering for the component you have created in the library(.OLB) was it Numeric or Alphabetic?

    Also, I just noticed SOT89 named footprint is present at sample location (C:\Cadence\SPB_23.1\share\pcb\pcb_lib\symbols) it might be causing the issue.

  • 0 in reply to Jeet

    In the .OLB, the part is designated "5V_AP7381-50Y-13_SOT89" with the foot print property set to "SOT89".

    I have other components added to the CIS-database that has different namnes but with the same footprint. Never any mismatch in those cases.

    In this case, the instantiation was for the component w/o any additional data such as MFR, MFR P/N etc. Placed schematic symbol. Footprint propertye automatically defined.

    The Cadence supplied libraries are omitted. In past times for the .OLB, the power pins were hidden with global nets which was not acceptable.

    Foot prints found in the \shared directories did have the same pad sizes for solder pads as for the solder masks. In Europe (or at least where I live), no automatic swelling is done by the board manufacturers. All data has to be "correct" when submitted except for traces where a tight impedance has to be maintained. (These traces are specified with a unique width and are used together with "coupons" for impedance verification after processing.

Reply
  • 0 in reply to Jeet

    In the .OLB, the part is designated "5V_AP7381-50Y-13_SOT89" with the foot print property set to "SOT89".

    I have other components added to the CIS-database that has different namnes but with the same footprint. Never any mismatch in those cases.

    In this case, the instantiation was for the component w/o any additional data such as MFR, MFR P/N etc. Placed schematic symbol. Footprint propertye automatically defined.

    The Cadence supplied libraries are omitted. In past times for the .OLB, the power pins were hidden with global nets which was not acceptable.

    Foot prints found in the \shared directories did have the same pad sizes for solder pads as for the solder masks. In Europe (or at least where I live), no automatic swelling is done by the board manufacturers. All data has to be "correct" when submitted except for traces where a tight impedance has to be maintained. (These traces are specified with a unique width and are used together with "coupons" for impedance verification after processing.

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