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Testprep...how to control distance from testvia to component pad.

steveO

I've tried to set the distance from a smd pin to a smd testvia but don't get the desired results. The distance ends up being via to smd pin which is smaller. How can i accomplish this without putting in a no-probe area around the pins? Thanks.

  • Did you set the spacing constraint from testvia to SMD pin in the constraint manager? Testprep should comply with the constraint set.
    Tomo

  • Yes I did. For this particular case, I set a padstack for the bottom side testpoint. it only had a pad on the END layer and a soldermask on the bottom. Then i added this to the available via's in CM. In Allegro, I routed out of one smd pad and added that via as a smd via. The question now is.....is that a testvia or just a regular via? it acts like a regular via. How do you make it a testvia if you add it manually?

  • Hi Steve,

    That is still not a testpoint via but just a normal via. A testpoint property needs to be added to the normal via.
    If you want to add the testpoint property to a via manually,
    Manufacture > Testprep  > Manual  (testprep  manual  command)
    However as a preliminary preparation, you will need to set the Testprep Parameters dialog box to determine the output of the automatic or manual testprep process by setting parameters.

    FYI
    http://www.cadence.com/Community/forums/p/4961/4970.aspx#4970

    Hope this helps.
    Tomo

  • tomoo, My parameter settings and padstack selection's have been set. i have also set the spacing in the constraint mgr. And i also have used the manual method to allocate a thru via as a testpoint. i've checked their properties. as far as a smd point, that's a different story. the way i do it is to add a via to a trace. in this case, i choose the surface mount pad from the via selection in the Options tab and change both layers to bottom in the Options tab. However, this way doesn't create a testpoint. i don't know how to create a smd testpoint using Testprep/Manual method. after the design is done however, i use the automatic method and it assigns that smd pad as a testpoint because it's in my padstack selections. Any help would be apprecated. Thanks.

  • Tomoo, I've since got Testprep to abide by the parameters and spacings set in CM. There is one thing though and that is why i can place a tp via within the placebound shape of a comp and yet i have stated in the parameters never to do that and use the placebound shape as the comp. representation. Any thoughts here?

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