Best practices for thermal pads with vias

I have been reviewing my company's footprints and found there are several different styles for the thermal pad, especially when vias are added. I'd like to see if there's a consensus on the best way to make footprints with thermal pads. Thanks in advance for any time to help me figure out if there is one superior way to do this.

There has been some related discussion here, but what I found was quite a few years old so Allegro may have changed since then. And I didn't find any suggestions in COS.

Here are the things I've noticed in our company library so far:

-Thermal pad copper element: Some thermal pads are actual pads, others are shapes.

-Via connectivity: Some vias are connected by a cline, others are just sitting in the pad or shape.

-"Via" type in thermal pad: Sometimes there is a single pin (for the symbol pin) and optionally multiple other vias for heatsinking, other times there are only vias.

-Paste layer (stencil) openings: The paste layer, if the thermal pad is large, should have several openings. I don't believe this can be done in a padstack.

-Symbol pin connection: The PACK_SHORT property is sometimes used to make a single symbol pin connect to multiple pins under the component. Other times there's a single symbol pin going to just a single element with connectivity in the footprint, with all other elements (vias and shapes and whatnot) deriving connectivity from that single element.

I'm sure there are other differences between our footprints with thermal pads that I haven't seen yet.

In several cases, I see DRC errors in the footprint. These may go away when the footprint is placed on a board, especially if the footprint is placed on a copper shape. However, if the footprint is placed in some empty area of the board and then moved on a shape there may be DRC errors. There can also be issues if the nets of the thermal pad and/or shape the footprint is placed change. I've haven't been able to fully figure this out but it's clear some footprints do better than others at picking up connectivity and not creating DRC errors in the board.

So... I ask you all. What works best? Is there a style that is understood to be superior? Maybe multiple approaches that are equally great?