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How to handle "unconnected pins" when they are apparently connected throught copper tracks?

EuSV

I have done a translation from old project to 16.6 orcad version. I have followed the whole of files traslation steps, importation, configurations, etc until I had no errors. I generated netlist and update the board layout. So looking to the pcb editor canvas it can be seen that there are some rastnets between pins that are connected because they have tracks connections. I followed the tracks, vias, etc path and there are electrical path. So I don't know how to solve this.

example: 

So I generated the unconnected pin report and this says that there is unconnected some of them, including the one seen at picture. I check the track names and all the segments forming the track path has the same net name. 

How can I deal with this? How can I do for looking the part that is not connected? can it be an interface mistake? I'm sure that the two pins has connection has a continuous track connection. 

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  • Eusv a couple of pointers.

    As Steve has pointed out Cadence handles a little differently how pins, vias, etch is connected. To make things easier it can be helpful to have a clearer look at the canvas so the nets that are not connected are easy to see.

    Here is a picture. "Turn Everything Off" leave pins and vias on. Go to "Setup Design Parameters" and uncheck filled pads. If the canvas is showing everything it can be hard to actually physically see connectivity issues. Change the ratsnest color to something really visible for example white so that the net shows up clearly.

    When you have the display less cluttered look around to see how many nets need to have connectivity fixed. Next run a report "Dangling Lines Via Antenna Report".

    The report will display showing the location of a problem with a line. In the picture you can see under "Dangling Line" the location of where the problem is. If you click on the location in the report the canvas will zoom and pan to where the issue is. The picture above shows that a net is not connected to the pin and this was derived from the report.

    To fix such problems a handy way of doing that is with the slide command. Under the find filter check Clines, Clines Segs. This will allow you to move the etch so it snaps to a pin or via. Click the slide icon and work around the board
    fixing the issues with the traces.

    Maybe give this a try and see how it works for you. When you get everything fixed "Run a DRC Check"

    All the best.

Reply

  • Eusv a couple of pointers.

    As Steve has pointed out Cadence handles a little differently how pins, vias, etch is connected. To make things easier it can be helpful to have a clearer look at the canvas so the nets that are not connected are easy to see.

    Here is a picture. "Turn Everything Off" leave pins and vias on. Go to "Setup Design Parameters" and uncheck filled pads. If the canvas is showing everything it can be hard to actually physically see connectivity issues. Change the ratsnest color to something really visible for example white so that the net shows up clearly.

    When you have the display less cluttered look around to see how many nets need to have connectivity fixed. Next run a report "Dangling Lines Via Antenna Report".

    The report will display showing the location of a problem with a line. In the picture you can see under "Dangling Line" the location of where the problem is. If you click on the location in the report the canvas will zoom and pan to where the issue is. The picture above shows that a net is not connected to the pin and this was derived from the report.

    To fix such problems a handy way of doing that is with the slide command. Under the find filter check Clines, Clines Segs. This will allow you to move the etch so it snaps to a pin or via. Click the slide icon and work around the board
    fixing the issues with the traces.

    Maybe give this a try and see how it works for you. When you get everything fixed "Run a DRC Check"

    All the best.

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