Footprints for Small Polarized Capacitors

Use PCB Editor to open the filename.dra of an 0805 then use Add - Text, set the Options pane to Package Geometry / Silkscreen_Top, the relevant text size and then add a + in text and position where you want this to go. I would then save the footprint as 0808_pol which saves a new filename.dra and filename.psm. Use this name for your pcb footprint going forward when you need a polarized cap.  

Thank you, Steve. It turns out that it is better to design a new footprint or redesign existing one. I just finished the Padstack editor tutorial and created my first SOIC8 for test. Really easy, as good as PADS.

Now I have a different question. In the folder "C:\Cadence\SPB_17.4\share\pcb\pcb_lib\symbols" there are thousands of probably useful footprints with absolutely confusing names. Is there any guide on the naming convention? Instead of calling them with human readable "SOIC8" or "TQFP64" they prefer "dax2850x225062.dra". There should be a good reason for such strange naming.

take a look at:- https://www.parallel-systems.co.uk/wp-content/uploads/2020/02/SPB172_Footprints-Parsys.pdf the names follow the ipc naming convention. 

take a look at:- https://www.parallel-systems.co.uk/wp-content/uploads/2020/02/SPB172_Footprints-Parsys.pdf the names follow the ipc naming convention. 

This is exactly what I was looking for. Thank you very much.

Now I am having another unexpected problem.

I tried to follow your advice and created a custom library with a copy of 'C' and 'Cap POL' of Discrete.Lib . Assigning of 'SMC1206' to 'C' works fine, however if I assign SMCT3216 to Cap  POL following message pops up whenever I try to import netlist to PCB editor:

ERROR(SPMHNI-196): Symbol 'SMCT3216' for device 'CAP POL_MY_0_SMCT3216_CAP POL_MY' has extra pin 'N'

Even if I rename Cap POL pins '1' and '2'  to 'P' and 'N' the message does not disappear.

You've got a mismatch somewhere.   Also, you might have a path issue.

One of the things about Allegro is that it caches the symbol (footprint) so having a netlist with one definition and a symbol with another gets tricky.  So here's a quick test:

In OrCAD, double-check to see that the pin NUMBER is 1,2  in the schematic.  Then in Allegro/OrCAD PCB open up the symbol for the cap and check the PIN number of each pin.  Then once both match, save the symbol as "SMCT3216_B" .  Go back to OrCAD and change the respective symbol PCB_FOOTPRINT property to "SMCT3216_B" as well.  Then re-netlist the design and bring in back into the PCB editor.  See if that corrects the issue.  

Thanks, this helped. I opened the 'smct3216.dra' and found that they use 'p' and 'N' not as pin names, but pin NUMBERS. After I used these confusing numbers in my copies of capacitor models the problem is gone. 

As a C programmer I can guess that they use uint8_t to store pin number and when the user enters 'P' the software reads it as 80 simply using ASCII value of the character. IMHO this is a bug. 

Glad you got it worked out.  It's those pesky details that bite us all.  Another issue to put in your files is pin 1,2 swapped on a polarized capacitor.  JEDEC has a definition of which pin should be negative and which one positive but often those get reversed and "poof" the polarized cap blows up because of mixups in the footprint vs the schematic.  Sigh.