Issue with impedance matching of differential pair

The guidance is a bit misleading.  You don't *require* 45 ohm single ended.  You do need 90 ohm differential.  The 90 ohm diff pair can be achieved with a tightly coupled pair on the top.  You could do CPWG as suggested by excelon or you can widen slightly and do just an edge-coupled microstrip pair.  

If you had a line which was 45 ohm single ended, and 90 ohm differential then that would suggest an uncoupled pair and those dimensions are not practical on a 2 layer board again as excelon has mentioned.

What tools were you using to check your impedance?  The calculator in Allegro/Orcad will get you the right values assuming your stackup has been entered correctly.

Okay!

Yes,I am using the calculator in Allegro/Orcad. I ma using same values but still not able to resolve the issue.

Thanks

Sugreev. My design did not use the impedance calculator in the cadence tool but was done on a RF Simulator.

So the first thing is you have to have manageable trace widths so as to route off the connector and to the IC you are using. I recalculated my initial design which had a trace width of 24 mils down to 13 mils so it would be easier to handle this. As Wild pointed out the impedance calculator in Allegro does not handle CPWG so don't worry about it.

For a DIFF Impedance target of 90 Ohms there are various combinations of trace to space and side wall ground that can be used.

On a pcb design most PCB tools use a "Global Impedance Calculation" Based on the stackup only. This has a huge caveat in a fair few regards.

Anyway to get to where you need to be the first thing is you want to remove the constraint for the impedance from the Allegro Spreadsheet.

Create a diff pair that has a trace width of 13 mils and a gap of 6 mils and route it in on the top layer.

Next add the ground either side of that diff pair. The spacing to the diff pair is 6mils. Just like in the picture above.

You can increase the spacing of the Ground Side wall to 10 mils. This will reduce the returnloss of the diff par a little but might make the design easier to manufacture.

Here is a pic of the Net Rules for the diff pair.

Before you add in the ground you want to set in the spreadsheet Your Line to Shape clearance and make it 6mils or 10 mils as explained above. This is done under the spacing > spacing constraint set - Shape to line setting.

In your picture it looks like you are just going a very short distance so things are less critical from the perspective of line signaling. If the 13 mil trace for the diff pair is too wide to come off the pins then go with

Trace width = 10 Mil
Trace Space =  6Mil
Trace to ground space = 6mil.

Update your constraints to accommodate the design spacing etc.

All the best.

Any chance you can post a zip of your board?  I also do as excellon says which means I use physical construction.  And, depending on how critical the impedance measurement needs to be I might have my fabricator do their own calculation to see what their final impedance value will be.  That's not really necessary for this design however.

I see that your "target" impedance is set to 90 and Cadence thinks it's 178(in the DRC).  That is telling me that Allegro is calculating with the wrong reference to the signal.

Red this is very curious. In 16.6 the stack up manager agrees fairly closely to the RF-Sim though it is off by 7 ohms or so. Not a big deal. By default that stackup manager assigns a dialectic constant to the conductor. Seems odd to do this but fudging that value of 4.5 to 8 brings the diff line impedance in line with the rf sim. Last I checked the dialectic constant of copper was infinity.

Plugging in a mask layer above reduces the impedance too.

Ignoring the CPWG for the moment and just going with std edge coupled lines  Cadence reports 103.34 Z for the diff pair using a trace width of 10Mil and space of 6mil.

When DRC reports your error is it reporting on the single line impedance or the actual calculated diff pair impedance ?. 178 divided by 2 = 89 which is very close to 90 ohms, assuming similar to what I have in the stackup.

I live more in the world of the physical than the CM for certain things but initially I got DRC errors too. My line impedance reported by the drc was based on the single line impedance. I had to plug in the single line impedance and not the actual required Diff-Pair impedance to make the drc go away. The DRC looks to report only single line impedance not the actual Diff-Pair as one would think if analysis mode is enabled for impedance.

Note the single line impedance matches the spreadsheet and all is good.

While I typically don't use the Stack up manager for impedance control for certain things it looks to me that while it can provide diff-pair info the DRC is all based on just the single line impedance only.

Maybe you can confirm that to be the case as a sanity check.

Thanks.

Hi excellon, I get the same results as you.  I was kind of hinting at the fact it was only single-ended based on the 90/180.  And now, from what I can see it appears that the impedance rule really only applies to the single-ended variant and CM does not understand a diff-pair impedance.

So...as you said earlier.  Stick with the physical rule definition... let's see if the OP has any more questions on that. 

Thank you Excellon and Redwire!

From all this what you have explained, I think that I have made mistake in setting the impedance of diff pair to 90 ohms in constraint manager.

In picture below, I have set the single-line impedance of the diff pair C-set to 90 ohms  in the electrical constraints. 

How much value should I set to the single-line impedance ?

Thank you Excellon and Redwire!

From all this what you have explained, I think that I have made mistake in setting the impedance of diff pair to 90 ohms in constraint manager.

In picture below, I have set the single-line impedance of the diff pair C-set to 90 ohms  in the electrical constraints. 

How much value should I set to the single-line impedance ?

Sugreev.

Since you are trying to design a diff pair on a STD 2Lyr board my suggestion to you is to not use the CM Impedance at all. "Disable it" it is not helping you !

Because you are trying to achieve a diff-pair of 90Z your best option is to go with what I indicated above and use physical design based on the board material instead.

The best option in your case is the coplainer waveguide.

Trace width = 10 Mil
Trace Space =  6Mil
Trace to top ground wall space = 6mil.
Remove the mask over the traces.

Just a FYI. The docs will tell you that a diff line impedance of 90 Ohms is required and this is correct. But in the real world your going to be adding maybe ESD protection to that transmission line
which will effect the impedance of the line. The app note goes into some good detail for that chip you wish to use. Perhaps dig in and read it very closely as it has some good info.

All the best.