• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Allegro X PCB Editor
  3. Test Point to Component Distance Report

Stats

  • Replies 12
  • Subscribers 161
  • Views 14054
  • Members are here 0
More Content

Test Point to Component Distance Report

obwise
obwise over 4 years ago

Hey guys

I was working on a test point to component csv parser file to see if I could find test points that were too close to each other according some clearance rules and the scope expanded beyond what i'm capable of right now on the software side of things.  While still working on this project for my own sake, I wanted to know if there was already a feature of OrCAD PCB Designer where I could see a report of test points that are too close to components or that would at least display distances between components, if they're on the top or bottom.  I would like the edge to edge distances between the test points and components.

  • Sign in to reply
  • Cancel
Parents
  • DavidJHutchins
    DavidJHutchins over 4 years ago

    Regarding the Valor NPI 'testpoint' analysis functionality, the list below is from 2009, I don't know if they added anything since then:

    “Testpoint to Testpoint (Spacing)”
    “Testpoint to Toeprint (Spacing)” 
    “Testpoint to Capped Via (Spacing)” 
    “Testpoint to Uncapped Via (Spacing)” 
    “Testpoint to Exposed Copper (Spacing)”
    “Testpoint to Exposed Copper (Primary) (Spacing)”
    “Testpoint to Exposed Copper (Secondary) (Spacing)” 
    “Testpoint to Unexposed Copper (Spacing)”
    “Testpoint Density (Spacing)”
    “Testpoint Density Under Component (Spacing)”
    “Testpoint to NPTH (Drill)” 
    “Testpoint to THMT Toeprint (Drill)”
    “Testpoint to Tooling Hole (Drill)” 
    “Testpoint to Rout (Rout)”
    “Testpoint to Conveyed Edge (Rout)” 
    “Testpoint to Non-Conveyed Edge (Rout)”
    “Testpoint Under Component (Component)” 
    “Testpoint to Component (Component)” 
    “Testpoint to Component Angle (Component)” 
    “Testpoint to SM (Solder Mask)”
    “Testpoint Missing Solderpaste (Solderpaste)”
    “Capped Testpoint Vias (Via Capping)”
    “Via Capped On Both Sides (Via Capping)” 
    “Uncapped Non-Testpoint Vias (Via Capping)”
    “Testpoints Outside Keepin Area (Keepin/Keepout)” 
    “Testpoints Within Keepout Area (Keepin/Keepout)”

    Then there is the 'DFT Testpoint Allocation Analysis' functionality, which adds the following:

    Nets without Potential Testpoints (Testpoint Allocation)
    Nets with One Potential Testpoint (Testpoint Allocation)
    Nets with Multiple Potential Testpoints (Testpoint Allocation)
    Potential Testpoints (Toeprint) (Testpoint Allocation)
    Potential Testpoints (Via) (Testpoint Allocation)
    Potential Testpoints (Other) (Testpoint Allocation)
    Potential Testpoint to Potential Testpoint (Distance) (Testpoint Allocation)
    Potential Testpoint to Potential Testpoint (Clearance) (Testpoint Allocation)
    Potential Testpoint to Exposed Copper (Testpoint Allocation)
    Potential Testpoint to NPTH (Testpoint Allocation)
    Potential Testpoint to Edge (Testpoint Allocation)
    Potential Testpoint under Component (Testpoint Allocation)
    Potential Testpoint to Component (Distance) (Testpoint Allocation)
    Potential Testpoint to Component (Clearance) (Testpoint Allocation)
    Probes to Component (Testpoint Allocation)
    Potential Testpoint Contact Diameter (Testpoint Allocation)
    Potential TP Large Pad (Testpoint Allocation)
    Potential Testpoint to Silk Screen (Testpoint Allocation)
    Potential Testpoint within Keepout Area (Testpoint Allocation)
    Potential Testpoint Not on Grid (Testpoint Allocation)

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
Reply
  • DavidJHutchins
    DavidJHutchins over 4 years ago

    Regarding the Valor NPI 'testpoint' analysis functionality, the list below is from 2009, I don't know if they added anything since then:

    “Testpoint to Testpoint (Spacing)”
    “Testpoint to Toeprint (Spacing)” 
    “Testpoint to Capped Via (Spacing)” 
    “Testpoint to Uncapped Via (Spacing)” 
    “Testpoint to Exposed Copper (Spacing)”
    “Testpoint to Exposed Copper (Primary) (Spacing)”
    “Testpoint to Exposed Copper (Secondary) (Spacing)” 
    “Testpoint to Unexposed Copper (Spacing)”
    “Testpoint Density (Spacing)”
    “Testpoint Density Under Component (Spacing)”
    “Testpoint to NPTH (Drill)” 
    “Testpoint to THMT Toeprint (Drill)”
    “Testpoint to Tooling Hole (Drill)” 
    “Testpoint to Rout (Rout)”
    “Testpoint to Conveyed Edge (Rout)” 
    “Testpoint to Non-Conveyed Edge (Rout)”
    “Testpoint Under Component (Component)” 
    “Testpoint to Component (Component)” 
    “Testpoint to Component Angle (Component)” 
    “Testpoint to SM (Solder Mask)”
    “Testpoint Missing Solderpaste (Solderpaste)”
    “Capped Testpoint Vias (Via Capping)”
    “Via Capped On Both Sides (Via Capping)” 
    “Uncapped Non-Testpoint Vias (Via Capping)”
    “Testpoints Outside Keepin Area (Keepin/Keepout)” 
    “Testpoints Within Keepout Area (Keepin/Keepout)”

    Then there is the 'DFT Testpoint Allocation Analysis' functionality, which adds the following:

    Nets without Potential Testpoints (Testpoint Allocation)
    Nets with One Potential Testpoint (Testpoint Allocation)
    Nets with Multiple Potential Testpoints (Testpoint Allocation)
    Potential Testpoints (Toeprint) (Testpoint Allocation)
    Potential Testpoints (Via) (Testpoint Allocation)
    Potential Testpoints (Other) (Testpoint Allocation)
    Potential Testpoint to Potential Testpoint (Distance) (Testpoint Allocation)
    Potential Testpoint to Potential Testpoint (Clearance) (Testpoint Allocation)
    Potential Testpoint to Exposed Copper (Testpoint Allocation)
    Potential Testpoint to NPTH (Testpoint Allocation)
    Potential Testpoint to Edge (Testpoint Allocation)
    Potential Testpoint under Component (Testpoint Allocation)
    Potential Testpoint to Component (Distance) (Testpoint Allocation)
    Potential Testpoint to Component (Clearance) (Testpoint Allocation)
    Probes to Component (Testpoint Allocation)
    Potential Testpoint Contact Diameter (Testpoint Allocation)
    Potential TP Large Pad (Testpoint Allocation)
    Potential Testpoint to Silk Screen (Testpoint Allocation)
    Potential Testpoint within Keepout Area (Testpoint Allocation)
    Potential Testpoint Not on Grid (Testpoint Allocation)

    • Cancel
    • Vote Up 0 Vote Down
    • Sign in to reply
    • Cancel
Children
No Data
Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information