Stats

  • Replies 6
  • Subscribers 162
  • Views 11705
  • Members are here 0
More Content

Test Point

Danilo Pichilli

Hi, I would like to insert test points on the bottom side of my pcb. But when I go to generate the gerber of the soldermask bottom I have to add the layer: "Via Class / soldermask bottom" to make sure that it does not have the soldermask on my final pcb in the test points. Unfortunately this causes me the absence of the soldermask also on the vias .. is there an alternative way to solve this problem? (I specify that the test point must be smd)

thanks

Parents
  • excellon1

    Hi try

    Via class / Soldermask_Bottom

    Pin /Soldermask_Bottom.

    That should work

  • Danilo Pichilli
    in reply to excellon1

    Thank for the reply, in fact with Via class / Soldermask_Bottom works. 

    the fact is: why allegro considers the test point as if it were a via and not a pin? 

  • RFinley
    in reply to Danilo Pichilli

    Testpoints are not netlist items from the schematic.   

    Every software I've used since Scicards, testpoints are vias with properties added that protect them.

Reply
  • RFinley
    in reply to Danilo Pichilli

    Testpoints are not netlist items from the schematic.   

    Every software I've used since Scicards, testpoints are vias with properties added that protect them.

Children
  • Wild
    in reply to RFinley

    A test point can be a part, it depends on your definition of what a test point is.  for example:

    https://www.digikey.com/en/products/detail/keystone-electronics/5023/5255493?s=N4IgjCBcpgHAzFUBjKAzAhgGwM4FMAaEAeygG0R5YAWWANlhAF0iAHAFyhAGV2AnAJYA7AOYgAvkQC0EaCFSRMuQiXKU6zcZJAAmNezw5OTcUA

    This part  is called a test point.

    We use Kobicon "test points"

    We use Keystone Test points

    We use unpopulated headers as test points.

    It is all in the definition of what you desire as a test point.

    So if I don't put these components in the schematic, how would I show them in the BOM, and the 3D assembly drawing?

  • Danilo Pichilli
    in reply to Wild

    Hi thanks for the reply... by test point I mean a point of the pcb where the track is interrupted by a circular pad without solder mask (therefore discovered) in which with my probe I go to carry out the measurements during the collapse phase.

  • Wild
    in reply to Danilo Pichilli

    I assumed that, but clarity is needed, others that read these forums may not understand what you are requesting.   If you google test points, a wiki page shows up:

    https://en.wikipedia.org/wiki/Test_point

    So I added this comment for the community to understand.

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.