Stats

More Content

How to add SMT test points ?

SOT23

Hello ! 

I am trying to add SMT test points to a board but couldn't find a way to do that. I tried : 

  • creating a single SMT pin footprint that I manually added, but I can't easily set a net to it to make it a test point.
  • creating a SMT via (just a 0.6mm circle on bottom layer), but I cannot add them to the board. I can add them to the Via list in the Physical Constraints Manager, but when I try to add them by using the Cline command (like I would do to add a THT via), it doesn't work, the SMT via doesn't appear in the list...

How could I simply add an SMT via to the board ?

Thank you !

Parents
  • SOT23
    0

    Still on the topic of Test Vias : 

    Does anyone know if it is possible to add a Placebound to a Test Vias ?

    I tried adding a layer in the padstack definition, but I cannot add constraint to it. Is it possible to define that layer so that it acts like a placebound ? 

  • jc teyssier
    0 in reply to SOT23

    For what purpose?

    To have a place boundady the test point have to be a component from schematic/netlist.

    If goal is only not to have tres point under compoennt, just set testpoint parameters correctly (do not allow under components)

Reply
  • jc teyssier
    0 in reply to SOT23

    For what purpose?

    To have a place boundady the test point have to be a component from schematic/netlist.

    If goal is only not to have tres point under compoennt, just set testpoint parameters correctly (do not allow under components)

Children
  • SOT23
    0 in reply to jc teyssier

    The goal is to avoid placing TPs to close to one another. I think it is nice to have a visual reference that the 2 TP you just placed are less than 1.27mm apart (or any other distance).

    In this picture I added a custom layer to the TP so that it displays some kind of "placebound" (I know it is not actually a placebound), this way, when I place my TP i know directly that there is enough space between them : 

    The "fake placebound" is a 1.27mm circle, so that I am sure that there is 1.27mm between 2 TP when these circles are touching.

    What I would like to do is add some kind of constraint to this layer so that it throws a DRC whenever the fake placebounds overlap.

    Here is how I defined it in the padstack editor : 

  • jc teyssier
    0 in reply to SOT23

    Can be done like this, yes

    But can be done also with the tool: in testprep parameters you can specify distance betwxeen TP's. Just do not forget to resequence tp's at the end (i personnaly resequence all during routing in order too know what is going on: it is verry quick)

    TP's too close will be removed,  reporting tp's will tell you nets without ones.

    Let have a loot to testprep parameters Slight smile

  • SOT23
    0 in reply to jc teyssier

    Yes, I know you can specify the distance, but at the moment you place the TP/via on the board, it is not yet a test via, you have to, either manually add a TP to that via, or do the automatic testprep. What I wanted is to be able to know directly, at the moment you place the via, if it is at the correct distance, without having to switch commands each and every time I put a via, but maybe it is a little bit to much to ask from Allegro ;)

Cadence Guidelines

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.